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Create synth_lattice

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This commit is contained in:
Miodrag Milanovic 2023-08-23 10:53:21 +02:00
parent a8809989c4
commit e3c15f003e
26 changed files with 4501 additions and 0 deletions
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techlibs/lattice/lutrams_map.v Normal file
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module $__TRELLIS_DPR16X4_(...);
parameter INIT = 64'bx;
parameter PORT_W_CLK_POL = 1;
input PORT_W_CLK;
input [3:0] PORT_W_ADDR;
input [3:0] PORT_W_WR_DATA;
input PORT_W_WR_EN;
input [3:0] PORT_R_ADDR;
output [3:0] PORT_R_RD_DATA;
localparam WCKMUX = PORT_W_CLK_POL ? "WCK" : "INV";
TRELLIS_DPR16X4 #(
.INITVAL(INIT),
.WCKMUX(WCKMUX),
.WREMUX("WRE")
) _TECHMAP_REPLACE_ (
.RAD(PORT_R_ADDR),
.DO(PORT_R_RD_DATA),
.WAD(PORT_W_ADDR),
.DI(PORT_W_WR_DATA),
.WCK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
endmodule