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Create synth_lattice

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Miodrag Milanovic 2023-08-23 10:53:21 +02:00
parent a8809989c4
commit e3c15f003e
26 changed files with 4501 additions and 0 deletions
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12
techlibs/lattice/lutrams.txt Normal file
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ram distributed $__TRELLIS_DPR16X4_ {
abits 4;
width 4;
cost 4;
init any;
prune_rom;
port sw "W" {
clock anyedge;
}
port ar "R" {
}
}