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Create synth_lattice

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Miodrag Milanovic 2023-08-23 10:53:21 +02:00
parent a8809989c4
commit e3c15f003e
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techlibs/lattice/latches_map.v Normal file
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module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule