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Create synth_lattice

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Miodrag Milanovic 2023-08-23 10:53:21 +02:00
parent a8809989c4
commit e3c15f003e
26 changed files with 4501 additions and 0 deletions
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50
techlibs/lattice/brams_8kc.txt Normal file
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ram block $__DP8KC_ {
abits 13;
widths 1 2 4 9 per_port;
cost 64;
init no_undef;
port srsw "A" "B" {
clock posedge;
clken;
portoption "WRITEMODE" "NORMAL" {
rdwr no_change;
}
portoption "WRITEMODE" "WRITETHROUGH" {
rdwr new;
}
portoption "WRITEMODE" "READBEFOREWRITE" {
rdwr old;
}
option "RESETMODE" "SYNC" {
rdsrst zero ungated block_wr;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
}
ram block $__PDPW8KC_ {
abits 13;
widths 1 2 4 9 18 per_port;
byte 9;
cost 64;
init no_undef;
port sr "R" {
clock posedge;
clken;
option "RESETMODE" "SYNC" {
rdsrst zero ungated;
}
option "RESETMODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
width 18;
clock posedge;
clken;
}
}