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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-06-02 18:47:14 +02:00 • committed by GitHub
commit e3a6b920d4
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8 changed files with 79 additions and 29 deletions
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10
tests/aiger/io.ys Normal file
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read_verilog <<EOF
module bad(
input in,
output reg [1:0] out
);
assign out = {in, 1'b0};
endmodule
EOF
proc
write_aiger -vmap /dev/null /dev/null

13
tests/svtypes/typedef_struct_global.ys Normal file
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read_verilog -sv << EOF
typedef struct packed {
logic y;
logic x;
} Vec_2_B;
module top;
Vec_2_B two_dee;
wire foo = two_dee.x;
endmodule
EOF