From 23c9828d7015ba9811e1dba08e2194fdf58e9497 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 9 Jan 2024 12:05:15 +0100
Subject: [PATCH 01/15] opt_clean: Remove dead branch

---
 passes/opt/opt_clean.cc | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 8b56895fe..19056e7e1 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -436,13 +436,6 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 		if (!raw_used_signals.check_any(s1)) {
 			// delete wires that aren't used by anything directly
 			goto delete_this_wire;
-		} else
-		if (!used_signals.check_any(s2)) {
-			// this path shouldn't be possible: this wire is used directly (otherwise it would get cleaned up above), and indirectly
-			// used wires are a superset of those used directly
-			log_assert(false);
-			// delete wires that aren't used by anything indirectly, even though other wires may alias it
-			goto delete_this_wire;
 		}
 
 		if (0)

From 158fbf881e0ba514e659e0e948491b045eab9f61 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Wed, 6 Mar 2024 15:15:37 +0100
Subject: [PATCH 02/15] memory_map: Explain `-iattr` better

---
 passes/memory/memory_map.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index cafc0aaf3..d1dd0fd88 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -415,7 +415,7 @@ struct MemoryMapPass : public Pass {
 		log("        to any of the values.\n");
 		log("\n");
 		log("    -iattr\n");
-		log("        for -attr, ignore case of <value>.\n");
+		log("        for -attr, suppress case sensitivity in matching of <value>.\n");
 		log("\n");
 		log("    -rom-only\n");
 		log("        only perform conversion for ROMs (memories with no write ports).\n");

From 858eae5572375fac376f6c2bb43e976abe73af0d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 8 Nov 2023 17:10:40 +0100
Subject: [PATCH 03/15] verific_const: convert VHDL values to RTLIL consts

---
 frontends/verific/verific.cc | 64 +++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 23 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index faa0e1bcd..6fc87ced6 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -223,7 +223,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 //
 // Note: For signed values, verific uses <len>'sb<bits> and decimal values can
 // also be negative.
-static const RTLIL::Const verific_const(const char *value, bool allow_string = true, bool output_signed = false)
+static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool allow_string = true, bool output_signed = false)
 {
 	size_t found;
 	char *end;
@@ -231,26 +231,44 @@ static const RTLIL::Const verific_const(const char *value, bool allow_string = t
 	bool is_signed = false;
 	RTLIL::Const c;
 	std::string val = std::string(value);
-	if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
-		c = RTLIL::Const(val.substr(1,val.size()-2));
-	} else if ((found = val.find("'sb")) != std::string::npos) {
-		is_signed = output_signed;
-		c = RTLIL::Const::from_string(val.substr(found + 3));
-	} else if ((found = val.find("'b")) != std::string::npos) {
-		c = RTLIL::Const::from_string(val.substr(found + 2));
-	} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
-			((decimal = std::strtol(value, &end, 10)), !end[0])) {
-		is_signed = output_signed;
-		c = RTLIL::Const((int)decimal, 32);
-	} else if (allow_string) {
-		c = RTLIL::Const(val);
+	if (from_vhdl) {
+		if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+			std::string data = val.substr(1,val.size()-2);
+			bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
+			if (isBinary)
+				c = RTLIL::Const::from_string(data);
+			else 
+				c = RTLIL::Const(data);
+		} else if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
+			c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+		} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
+				((decimal = std::strtol(value, &end, 10)), !end[0])) {
+			is_signed = output_signed;
+			c = RTLIL::Const((int)decimal, 32);
+		} else {
+			log_error("non-expected '%s' constant found", value);
+		}
 	} else {
-		log_error("expected numeric constant but found '%s'", value);
+		if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+			c = RTLIL::Const(val.substr(1,val.size()-2));
+		} else if ((found = val.find("'sb")) != std::string::npos) {
+			is_signed = output_signed;
+			c = RTLIL::Const::from_string(val.substr(found + 3));
+		} else if ((found = val.find("'b")) != std::string::npos) {
+			c = RTLIL::Const::from_string(val.substr(found + 2));
+		} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
+				((decimal = std::strtol(value, &end, 10)), !end[0])) {
+			is_signed = output_signed;
+			c = RTLIL::Const((int)decimal, 32);
+		} else if (allow_string) {
+			c = RTLIL::Const(val);
+		} else {
+			log_error("expected numeric constant but found '%s'", value);
+		}
+
+		if (is_signed)
+			c.flags |= RTLIL::CONST_FLAG_SIGNED;
 	}
-
-	if (is_signed)
-		c.flags |= RTLIL::CONST_FLAG_SIGNED;
-
 	return c;
 }
 
@@ -276,7 +294,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 	FOREACH_ATTRIBUTE(obj, mi, attr) {
 		if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
 			continue;
-		attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value());
+		attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value(), obj->IsFromVhdl());
 	}
 
 	if (nl) {
@@ -298,7 +316,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 		const char *k, *v;
 		FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
 			if (nl->IsFromVerilog()) {
-				auto const value = verific_const(v, false);
+				auto const value = verific_const(v, nl->IsFromVhdl(), false);
 
 				attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k));
 			}
@@ -1304,7 +1322,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	MapIter mi;
 	FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
 		module->avail_parameters(RTLIL::escape_id(param_name));
-		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value);
+		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value, nl->IsFromVhdl());
 	}
 
 	SetIter si;
@@ -2004,7 +2022,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		const char *param_value ;
 		if (is_blackbox(inst->View())) {
 			FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) {
-				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value));
+				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value, nl->IsFromVhdl()));
 			}
 		}
 

From 4279cea33a91aa934f65072e7b6c34830f55b037 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 11 Mar 2024 09:30:58 +0100
Subject: [PATCH 04/15] improve handling VHDL constants

---
 frontends/verific/verific.cc | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6fc87ced6..6dbad4c2a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -223,7 +223,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 //
 // Note: For signed values, verific uses <len>'sb<bits> and decimal values can
 // also be negative.
-static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool allow_string = true, bool output_signed = false)
+static const RTLIL::Const verific_const(const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
 {
 	size_t found;
 	char *end;
@@ -231,7 +231,7 @@ static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool
 	bool is_signed = false;
 	RTLIL::Const c;
 	std::string val = std::string(value);
-	if (from_vhdl) {
+	if (obj->IsFromVhdl()) {
 		if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
 			std::string data = val.substr(1,val.size()-2);
 			bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
@@ -245,6 +245,10 @@ static const RTLIL::Const verific_const(const char *value, bool from_vhdl, bool
 				((decimal = std::strtol(value, &end, 10)), !end[0])) {
 			is_signed = output_signed;
 			c = RTLIL::Const((int)decimal, 32);
+		} else if (val == "false") {
+			c = RTLIL::Const::from_string("0");
+		} else if (val == "true") {
+			c = RTLIL::Const::from_string("1");
 		} else {
 			log_error("non-expected '%s' constant found", value);
 		}
@@ -294,7 +298,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 	FOREACH_ATTRIBUTE(obj, mi, attr) {
 		if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
 			continue;
-		attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value(), obj->IsFromVhdl());
+		attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value(), obj);
 	}
 
 	if (nl) {
@@ -316,7 +320,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 		const char *k, *v;
 		FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
 			if (nl->IsFromVerilog()) {
-				auto const value = verific_const(v, nl->IsFromVhdl(), false);
+				auto const value = verific_const(v, nl, false);
 
 				attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k));
 			}
@@ -1322,7 +1326,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	MapIter mi;
 	FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
 		module->avail_parameters(RTLIL::escape_id(param_name));
-		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value, nl->IsFromVhdl());
+		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value, nl);
 	}
 
 	SetIter si;
@@ -2022,7 +2026,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		const char *param_value ;
 		if (is_blackbox(inst->View())) {
 			FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) {
-				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value, nl->IsFromVhdl()));
+				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value, inst->View()));
 			}
 		}
 

From 7c09fa572e2eb4cce2cfdfcfdbc7ca327382ad2a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 14 Mar 2024 10:37:11 +0100
Subject: [PATCH 05/15] real number handling and default to string

---
 frontends/verific/verific.cc | 50 +++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 12 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 6dbad4c2a..a5bcd44c4 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -214,6 +214,22 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 	return s;
 }
 
+RTLIL::Const mkconst_str(const std::string &str)
+{
+	RTLIL::Const val;
+	std::vector<RTLIL::State> data;
+	data.reserve(str.size() * 8);
+	for (size_t i = 0; i < str.size(); i++) {
+		unsigned char ch = str[str.size() - i - 1];
+		for (int j = 0; j < 8; j++) {
+			data.push_back((ch & 1) ? State::S1 : State::S0);
+			ch = ch >> 1;
+		}
+	}
+	val.bits = data;
+	val.flags |= RTLIL::CONST_FLAG_STRING;
+	return val;
+}
 // When used as attributes or parameter values Verific constants come already processed.
 // - Real string values are already under quotes
 // - Numeric values with specified width are always converted to binary
@@ -223,7 +239,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
 //
 // Note: For signed values, verific uses <len>'sb<bits> and decimal values can
 // also be negative.
-static const RTLIL::Const verific_const(const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
+static const RTLIL::Const verific_const(const char* type_name, const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
 {
 	size_t found;
 	char *end;
@@ -232,7 +248,10 @@ static const RTLIL::Const verific_const(const char *value, DesignObj *obj, bool
 	RTLIL::Const c;
 	std::string val = std::string(value);
 	if (obj->IsFromVhdl()) {
-		if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		if (type_name && strcmp(type_name, "real")==0) {
+			c = mkconst_str(val);
+			c.flags |= RTLIL::CONST_FLAG_REAL;
+		} else if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
 			std::string data = val.substr(1,val.size()-2);
 			bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
 			if (isBinary)
@@ -250,10 +269,14 @@ static const RTLIL::Const verific_const(const char *value, DesignObj *obj, bool
 		} else if (val == "true") {
 			c = RTLIL::Const::from_string("1");
 		} else {
-			log_error("non-expected '%s' constant found", value);
+			c = mkconst_str(val);
+			log_warning("encoding value '%s' of type '%s' as string  found", value, type_name ? type_name : "unknown");
 		}
 	} else {
-		if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		if (type_name && strcmp(type_name, "real")==0) {
+			c = mkconst_str(val);
+			c.flags |= RTLIL::CONST_FLAG_REAL;
+		} else if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
 			c = RTLIL::Const(val.substr(1,val.size()-2));
 		} else if ((found = val.find("'sb")) != std::string::npos) {
 			is_signed = output_signed;
@@ -267,12 +290,13 @@ static const RTLIL::Const verific_const(const char *value, DesignObj *obj, bool
 		} else if (allow_string) {
 			c = RTLIL::Const(val);
 		} else {
-			log_error("expected numeric constant but found '%s'", value);
+			c = mkconst_str(val);
+			log_warning("encoding value '%s' of type '%s' as string  found", value, type_name ? type_name : "unknown");
 		}
-
-		if (is_signed)
-			c.flags |= RTLIL::CONST_FLAG_SIGNED;
 	}
+
+	if (is_signed)
+		c.flags |= RTLIL::CONST_FLAG_SIGNED;
 	return c;
 }
 
@@ -298,7 +322,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 	FOREACH_ATTRIBUTE(obj, mi, attr) {
 		if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
 			continue;
-		attributes[RTLIL::escape_id(attr->Key())] = verific_const(attr->Value(), obj);
+		attributes[RTLIL::escape_id(attr->Key())] = verific_const(nullptr, attr->Value(), obj);
 	}
 
 	if (nl) {
@@ -320,7 +344,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
 		const char *k, *v;
 		FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
 			if (nl->IsFromVerilog()) {
-				auto const value = verific_const(v, nl, false);
+				auto const value = verific_const(type_name, v, nl, false);
 
 				attributes.emplace(stringf("\\enum_value_%s", value.as_string().c_str()), RTLIL::escape_id(k));
 			}
@@ -1326,7 +1350,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	MapIter mi;
 	FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) {
 		module->avail_parameters(RTLIL::escape_id(param_name));
-		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(param_value, nl);
+		const TypeRange *tr = nl->GetTypeRange(param_name) ;
+		module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(tr->GetTypeName(), param_value, nl);
 	}
 
 	SetIter si;
@@ -2026,7 +2051,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		const char *param_value ;
 		if (is_blackbox(inst->View())) {
 			FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) {
-				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value, inst->View()));
+				const TypeRange *tr = inst->View()->GetTypeRange(param_name) ;
+				cell->setParam(RTLIL::escape_id(param_name), verific_const(tr->GetTypeName(), param_value, inst->View()));
 			}
 		}
 

From 9eebc801705c6f7c179f354774b9d87174b3ec3f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 18 Mar 2024 10:35:01 +0100
Subject: [PATCH 06/15] handle standard types

---
 frontends/verific/verific.cc | 47 +++++++++++++++++++++++++++++++++---
 1 file changed, 44 insertions(+), 3 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index a5bcd44c4..62c070db5 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -248,9 +248,50 @@ static const RTLIL::Const verific_const(const char* type_name, const char *value
 	RTLIL::Const c;
 	std::string val = std::string(value);
 	if (obj->IsFromVhdl()) {
-		if (type_name && strcmp(type_name, "real")==0) {
-			c = mkconst_str(val);
-			c.flags |= RTLIL::CONST_FLAG_REAL;
+		if (type_name) {
+			if (strcmp(type_name, "integer")==0 ||  strcmp(type_name, "natural")==0 || strcmp(type_name, "positive")==0) {
+				decimal = std::strtol(value, &end, 10);
+				c = RTLIL::Const((int)decimal, 32);
+			} else if (strcmp(type_name, "boolean")==0) {
+				if (val == "false") {
+					c = RTLIL::Const::from_string("0");
+				} else if (val == "true") {
+					c = RTLIL::Const::from_string("1");
+				} else 
+					log_error("Error parsing boolean\n");
+			} else if (strcmp(type_name, "bit")==0 || strcmp(type_name, "STD_LOGIC")==0 || strcmp(type_name, "STD_ULOGIC")==0) {
+				if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
+					c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+				} else 
+					log_error("Error parsing %s\n", type_name);
+			} else if (strcmp(type_name, "character")==0) {
+				if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+					c = RTLIL::Const((int)val[1], 32);
+				} else 
+					log_error("Error parsing character\n");
+			} else if (strcmp(type_name, "bit_vector")==0 || strcmp(type_name, "STD_LOGIC_VECTOR")==0 || strcmp(type_name, "STD_ULOGIC_VECTOR")==0 ||
+					   strcmp(type_name, "UNSIGNED")==0 || strcmp(type_name, "SIGNED")==0) {
+				if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+					c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+				} else 
+					log_error("Error parsing %s\n", type_name);
+				if (strcmp(type_name, "SIGNED")==0)
+					is_signed = true;
+			} else if (strcmp(type_name, "real")==0) {
+				c = mkconst_str(val);
+				c.flags |= RTLIL::CONST_FLAG_REAL;
+			} else if (strcmp(type_name, "string")==0) {
+				if (!(val.size()>1 && val[0]=='\"' && val.back()=='\"'))
+					log_error("Error parsing string\n");
+				c = RTLIL::Const(val.substr(1,val.size()-2));
+			} else {
+				if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
+					c = RTLIL::Const(val.substr(1,val.size()-2));
+				else if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
+					c = RTLIL::Const(val.substr(1,val.size()-2));
+				else
+					c = RTLIL::Const(val);
+			}
 		} else if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
 			std::string data = val.substr(1,val.size()-2);
 			bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });

From 4367e176fbfcfc3722dfa4a7a12c66cd430e3bf5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 19 Mar 2024 09:15:04 +0100
Subject: [PATCH 07/15] code split and cleanup

---
 frontends/verific/verific.cc | 231 +++++++++++++++++++++--------------
 1 file changed, 141 insertions(+), 90 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 62c070db5..96e0469f6 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -230,6 +230,126 @@ RTLIL::Const mkconst_str(const std::string &str)
 	val.flags |= RTLIL::CONST_FLAG_STRING;
 	return val;
 }
+
+static const RTLIL::Const extract_vhdl_boolean(std::string &val)
+{
+	if (val == "false")
+		return RTLIL::Const::from_string("0");
+	if (val == "true")
+		return RTLIL::Const::from_string("1");
+	log_error("Expecting VHDL boolean value.\n");
+}
+
+static const RTLIL::Const extract_vhdl_bit(std::string &val, std::string &typ)
+{
+	if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
+		return  RTLIL::Const::from_string(val.substr(1,val.size()-2));
+	log_error("Error parsing VHDL %s.\n", typ.c_str());
+}
+
+static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string &typ)
+{
+	if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		RTLIL::Const c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+		if (typ == "signed")
+			c.flags |= RTLIL::CONST_FLAG_SIGNED;
+		return c;
+	}
+	log_error("Error parsing VHDL %s.\n", typ.c_str());
+}
+
+static const RTLIL::Const extract_vhdl_integer(std::string &val)
+{
+	char *end;
+	return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10), 32);
+}
+
+static const RTLIL::Const extract_vhdl_char(std::string &val)
+{
+	if (val.size()==3 && val[0]=='\"' && val.back()=='\"')
+		return RTLIL::Const((int)val[1], 32);
+	log_error("Error parsing VHDL character.\n");
+}
+
+static const RTLIL::Const extract_real_value(std::string &val)
+{
+	RTLIL::Const c = mkconst_str(val);
+	c.flags |= RTLIL::CONST_FLAG_REAL;
+	return c;
+}
+
+static const RTLIL::Const extract_vhdl_string(std::string &val)
+{
+	if (!(val.size()>1 && val[0]=='\"' && val.back()=='\"'))
+		log_error("Error parsing VHDL string.\n");
+	return RTLIL::Const(val.substr(1,val.size()-2));
+}
+
+static const  RTLIL::Const extract_vhdl_const(const char *value, bool output_signed)
+{
+	RTLIL::Const c;
+	char *end;
+	int decimal;
+	bool is_signed = false;
+	std::string val = std::string(value);
+
+	if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		std::string data = val.substr(1,val.size()-2);
+		bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
+		if (isBinary)
+			c = RTLIL::Const::from_string(data);
+		else 
+			c = RTLIL::Const(data);
+	} else if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
+		c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
+	} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
+			((decimal = std::strtol(value, &end, 10)), !end[0])) {
+		is_signed = output_signed;
+		c = RTLIL::Const((int)decimal, 32);
+	} else if (val == "false") {
+		c = RTLIL::Const::from_string("0");
+	} else if (val == "true") {
+		c = RTLIL::Const::from_string("1");
+	} else {
+		c = mkconst_str(val);
+		log_warning("encoding value '%s' as string.\n", value);
+	}
+	if (is_signed)
+		c.flags |= RTLIL::CONST_FLAG_SIGNED;
+	return c;
+}
+
+static const  RTLIL::Const extract_verilog_const(const char *value, bool allow_string, bool output_signed)
+{
+	RTLIL::Const c;
+	char *end;
+	int decimal;
+	bool is_signed = false;
+	size_t found;
+	std::string val = std::string(value);
+
+	if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
+		c = RTLIL::Const(val.substr(1,val.size()-2));
+	} else if ((found = val.find("'sb")) != std::string::npos) {
+		is_signed = output_signed;
+		c = RTLIL::Const::from_string(val.substr(found + 3));
+	} else if ((found = val.find("'b")) != std::string::npos) {
+		c = RTLIL::Const::from_string(val.substr(found + 2));
+	} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
+			((decimal = std::strtol(value, &end, 10)), !end[0])) {
+		is_signed = output_signed;
+		c = RTLIL::Const((int)decimal, 32);
+	} else if (allow_string) {
+		c = RTLIL::Const(val);
+	} else {
+		c = mkconst_str(val);
+		log_warning("encoding value '%s' as string.\n", value);
+	}
+	if (is_signed)
+		c.flags |= RTLIL::CONST_FLAG_SIGNED;
+	return c;
+}
+
 // When used as attributes or parameter values Verific constants come already processed.
 // - Real string values are already under quotes
 // - Numeric values with specified width are always converted to binary
@@ -241,104 +361,35 @@ RTLIL::Const mkconst_str(const std::string &str)
 // also be negative.
 static const RTLIL::Const verific_const(const char* type_name, const char *value, DesignObj *obj, bool allow_string = true, bool output_signed = false)
 {
-	size_t found;
-	char *end;
-	int decimal;
-	bool is_signed = false;
-	RTLIL::Const c;
 	std::string val = std::string(value);
+	// VHDL
 	if (obj->IsFromVhdl()) {
 		if (type_name) {
-			if (strcmp(type_name, "integer")==0 ||  strcmp(type_name, "natural")==0 || strcmp(type_name, "positive")==0) {
-				decimal = std::strtol(value, &end, 10);
-				c = RTLIL::Const((int)decimal, 32);
-			} else if (strcmp(type_name, "boolean")==0) {
-				if (val == "false") {
-					c = RTLIL::Const::from_string("0");
-				} else if (val == "true") {
-					c = RTLIL::Const::from_string("1");
-				} else 
-					log_error("Error parsing boolean\n");
-			} else if (strcmp(type_name, "bit")==0 || strcmp(type_name, "STD_LOGIC")==0 || strcmp(type_name, "STD_ULOGIC")==0) {
-				if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
-					c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
-				} else 
-					log_error("Error parsing %s\n", type_name);
-			} else if (strcmp(type_name, "character")==0) {
-				if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
-					c = RTLIL::Const((int)val[1], 32);
-				} else 
-					log_error("Error parsing character\n");
-			} else if (strcmp(type_name, "bit_vector")==0 || strcmp(type_name, "STD_LOGIC_VECTOR")==0 || strcmp(type_name, "STD_ULOGIC_VECTOR")==0 ||
-					   strcmp(type_name, "UNSIGNED")==0 || strcmp(type_name, "SIGNED")==0) {
-				if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
-					c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
-				} else 
-					log_error("Error parsing %s\n", type_name);
-				if (strcmp(type_name, "SIGNED")==0)
-					is_signed = true;
-			} else if (strcmp(type_name, "real")==0) {
-				c = mkconst_str(val);
-				c.flags |= RTLIL::CONST_FLAG_REAL;
-			} else if (strcmp(type_name, "string")==0) {
-				if (!(val.size()>1 && val[0]=='\"' && val.back()=='\"'))
-					log_error("Error parsing string\n");
-				c = RTLIL::Const(val.substr(1,val.size()-2));
-			} else {
+			std::string typ = std::string(type_name);
+			transform(typ.begin(), typ.end(), typ.begin(), ::tolower);
+			if (typ ==  "integer" ||  typ == "natural" || typ=="positive") return extract_vhdl_integer(val);
+			else if (typ =="boolean") return extract_vhdl_boolean(val);
+			else if (typ == "bit" || typ =="std_logic" || typ == "std_ulogic") return extract_vhdl_bit(val,typ);
+			else if (typ == "character") return extract_vhdl_char(val);
+			else if (typ == "bit_vector" || typ == "std_logic_vector" || typ == "std_ulogic_vector" ||
+					 typ == "unsigned" || typ == "signed") return extract_vhdl_bit_vector(val,typ);
+			else if (typ == "real") return extract_real_value(val);
+			else if (typ == "string") return extract_vhdl_string(val);
+			else {
 				if (val.size()>1 && val[0]=='\"' && val.back()=='\"')
-					c = RTLIL::Const(val.substr(1,val.size()-2));
+					return RTLIL::Const(val.substr(1,val.size()-2));
 				else if (val.size()==3 && val[0]=='\'' && val.back()=='\'')
-					c = RTLIL::Const(val.substr(1,val.size()-2));
+					return RTLIL::Const(val.substr(1,val.size()-2));
 				else
-					c = RTLIL::Const(val);
+					return RTLIL::Const(val);
 			}
-		} else if (val.size()>1 && val[0]=='\"' && val.back()=='\"') {
-			std::string data = val.substr(1,val.size()-2);
-			bool isBinary = std::all_of(data.begin(), data.end(), [](char c) {return c=='1' || c=='0'; });
-			if (isBinary)
-				c = RTLIL::Const::from_string(data);
-			else 
-				c = RTLIL::Const(data);
-		} else if (val.size()==3 && val[0]=='\'' && val.back()=='\'') {
-			c = RTLIL::Const::from_string(val.substr(1,val.size()-2));
-		} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
-				((decimal = std::strtol(value, &end, 10)), !end[0])) {
-			is_signed = output_signed;
-			c = RTLIL::Const((int)decimal, 32);
-		} else if (val == "false") {
-			c = RTLIL::Const::from_string("0");
-		} else if (val == "true") {
-			c = RTLIL::Const::from_string("1");
-		} else {
-			c = mkconst_str(val);
-			log_warning("encoding value '%s' of type '%s' as string  found", value, type_name ? type_name : "unknown");
-		}
-	} else {
-		if (type_name && strcmp(type_name, "real")==0) {
-			c = mkconst_str(val);
-			c.flags |= RTLIL::CONST_FLAG_REAL;
-		} else if (allow_string && val.size()>1 && val[0]=='\"' && val.back()=='\"') {
-			c = RTLIL::Const(val.substr(1,val.size()-2));
-		} else if ((found = val.find("'sb")) != std::string::npos) {
-			is_signed = output_signed;
-			c = RTLIL::Const::from_string(val.substr(found + 3));
-		} else if ((found = val.find("'b")) != std::string::npos) {
-			c = RTLIL::Const::from_string(val.substr(found + 2));
-		} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
-				((decimal = std::strtol(value, &end, 10)), !end[0])) {
-			is_signed = output_signed;
-			c = RTLIL::Const((int)decimal, 32);
-		} else if (allow_string) {
-			c = RTLIL::Const(val);
-		} else {
-			c = mkconst_str(val);
-			log_warning("encoding value '%s' of type '%s' as string  found", value, type_name ? type_name : "unknown");
-		}
+		} else extract_vhdl_const(value, output_signed);
 	}
-
-	if (is_signed)
-		c.flags |= RTLIL::CONST_FLAG_SIGNED;
-	return c;
+	// SystemVerilog
+	if (type_name && strcmp(type_name, "real")==0) {
+		return extract_real_value(val);
+	} else 
+		return extract_verilog_const(value, allow_string, output_signed);
 }
 
 static const std::string verific_unescape(const char *value)

From f536de0e0e585fe3c6146bc7e8f1a4d3b0e14bc4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 28 Mar 2024 13:21:55 +0100
Subject: [PATCH 08/15] Verific support for VHDL 2019

---
 frontends/verific/Makefile.inc |  1 +
 frontends/verific/verific.cc   | 29 ++++++++++++++++++++++++++---
 2 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/frontends/verific/Makefile.inc b/frontends/verific/Makefile.inc
index c82428613..df3ac8d2d 100644
--- a/frontends/verific/Makefile.inc
+++ b/frontends/verific/Makefile.inc
@@ -14,6 +14,7 @@ ifneq ($(DISABLE_VERIFIC_VHDL),1)
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1987/. share/verific.new/vhdl_vdbs_1987
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_1993/. share/verific.new/vhdl_vdbs_1993
 	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2008/. share/verific.new/vhdl_vdbs_2008
+	$(Q) cp -r $(VERIFIC_DIR)/vhdl_packages/vdbs_2019/. share/verific.new/vhdl_vdbs_2019
 endif
 	$(Q) chmod -R a+rX share/verific.new
 	$(Q) mv share/verific.new share/verific
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index faa0e1bcd..a65fde42f 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2699,7 +2699,7 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("\n");
 #ifdef VERIFIC_VHDL_SUPPORT
-		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
+		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files into Verific.\n");
 		log("\n");
@@ -3436,6 +3436,29 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2019")) {
+			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2019").c_str());
+			bool flag_lib = false;
+			for (argidx++; argidx < GetSize(args); argidx++) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
+				Map map(POINTER_HASH);
+				add_units_to_map(map, work, flag_lib);
+				std::string filename = frontent_rewrite(args, argidx, tmp_files);
+				if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2019))
+					log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename.c_str());
+				set_units_to_blackbox(map, work, flag_lib);
+			}
+			verific_import_pending = true;
+			goto check_error;
+		}
+
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
 			bool flag_lib = false;
@@ -3979,7 +4002,7 @@ struct ReadPass : public Pass {
 		log("\n");
 		log("\n");
 #ifdef VERIFIC_VHDL_SUPPORT
-		log("    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
+		log("    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl2019|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files. (Requires Verific.)\n");
 		log("\n");
@@ -4083,7 +4106,7 @@ struct ReadPass : public Pass {
 		}
 
 #ifdef VERIFIC_VHDL_SUPPORT
-		if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") {
+		if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl2019" || args[1] == "-vhdl") {
 			if (use_verific) {
 				args[0] = "verific";
 				Pass::call(design, args);

From 4bb3b099d23b07e0b4f8cf85e7b426be1538fafa Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 3 Apr 2024 10:02:53 +0200
Subject: [PATCH 09/15] opt_demorgan: fix extra args warning

---
 passes/opt/opt_demorgan.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
index 1464c4177..4db3a8101 100644
--- a/passes/opt/opt_demorgan.cc
+++ b/passes/opt/opt_demorgan.cc
@@ -183,7 +183,7 @@ struct OptDemorganPass : public Pass {
 	{
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
 
-		int argidx = 0;
+		int argidx = 1;
 		extra_args(args, argidx, design);
 
 		unsigned int cells_changed = 0;

From a1bb0255d654ffd0d8503577274f24b349a42995 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 10 Apr 2024 08:17:27 +0200
Subject: [PATCH 10/15] Release version 0.40

---
 CHANGELOG | 13 ++++++++++++-
 Makefile  |  4 ++--
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index b172988d5..ba734fb35 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,8 +2,19 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.39 .. Yosys 0.40-dev
+Yosys 0.39 .. Yosys 0.40
 --------------------------
+ * New commands and options
+    - Added option "-vhdl2019" to "read" and "verific" pass. 
+
+ * Various
+    - Major documentation overhaul.
+    - Added port statistics to "stat" command.
+    - Added new formatting features to cxxrtl backend.
+
+ * Verific support
+    - Added better support for VHDL constants import.
+    - Added support for VHDL 2009.
 
 Yosys 0.38 .. Yosys 0.39
 --------------------------
diff --git a/Makefile b/Makefile
index f8d628010..e7ed6c9fe 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.39+183
+YOSYS_VER := 0.40
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -158,7 +158,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0033808.. | wc -l`/;" Makefile
+#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0033808.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #

From e01e942f81bee11ff5f000cde9970f08f97b12b6 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 10 Apr 2024 08:21:35 +0200
Subject: [PATCH 11/15] Next dev cycle

---
 CHANGELOG | 3 +++
 Makefile  | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index ba734fb35..f42eaca27 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 List of major changes and improvements between releases
 =======================================================
 
+Yosys 0.40 .. Yosys 0.41-dev
+--------------------------
+
 Yosys 0.39 .. Yosys 0.40
 --------------------------
  * New commands and options
diff --git a/Makefile b/Makefile
index e7ed6c9fe..6d81b627f 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.40
+YOSYS_VER := 0.40+0
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -158,7 +158,7 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-#	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 0033808.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline a1bb025.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #

From e2cfcbcf25afc9062d0f85748ab908c7ced71d81 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 10 Apr 2024 10:12:05 +0200
Subject: [PATCH 12/15] fix .gitignore

---
 docs/source/code_examples/extensions/.gitignore | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/source/code_examples/extensions/.gitignore b/docs/source/code_examples/extensions/.gitignore
index ccdd6bd5c..675a532ed 100644
--- a/docs/source/code_examples/extensions/.gitignore
+++ b/docs/source/code_examples/extensions/.gitignore
@@ -1,2 +1,3 @@
 my_cmd.so
 my_cmd.d
+*.log

From 47bdb3e32f71add7a48ec6215e9838048d52609a Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Thu, 11 Apr 2024 00:16:34 +0000
Subject: [PATCH 13/15] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 6d81b627f..6d7bb2cec 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.40+0
+YOSYS_VER := 0.40+4
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

From 0c7ac36dcf18ed1afcb2ef5a3011c2a47b8d4118 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 11 Apr 2024 14:56:00 +0200
Subject: [PATCH 14/15] Add workflows and CODEOWNERS and fixed gitignore

---
 CODEOWNERS                       | 3 ++-
 tests/arch/quicklogic/.gitignore | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/CODEOWNERS b/CODEOWNERS
index 7d680e9f2..879bb8dee 100644
--- a/CODEOWNERS
+++ b/CODEOWNERS
@@ -10,6 +10,7 @@
 
 # PATH (can use glob)          USERNAME(S)
 
+CODEOWNERS                     @nakengelhardt
 passes/cmds/scratchpad.cc      @nakengelhardt
 frontends/rpc/                 @whitequark
 backends/cxxrtl/               @whitequark
@@ -19,7 +20,7 @@ passes/opt/opt_lut.cc          @whitequark
 passes/techmap/abc9*.cc        @eddiehung @Ravenslofty
 backends/aiger/xaiger.cc       @eddiehung
 docs/                          @KrystalDelusion
-
+.github/workflows/*.yml        @mmicko
 
 ## External Contributors
 # Only users with write permission to the repository get review
diff --git a/tests/arch/quicklogic/.gitignore b/tests/arch/quicklogic/.gitignore
index 9a71dca69..ae20ed342 100644
--- a/tests/arch/quicklogic/.gitignore
+++ b/tests/arch/quicklogic/.gitignore
@@ -1,4 +1,4 @@
 *.log
-/run-test.mk
+run-test.mk
 +*_synth.v
 +*_testbench

From ed46453cfc3032d28246e81d93bfb8a8c65f826e Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sat, 13 Apr 2024 00:14:07 +0000
Subject: [PATCH 15/15] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 6d7bb2cec..04cb5edc2 100644
--- a/Makefile
+++ b/Makefile
@@ -142,7 +142,7 @@ LIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.40+4
+YOSYS_VER := 0.40+7
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo