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Merge pull request #1147 from YosysHQ/clifford/fix1144

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Improve specify dummy parser
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Clifford Wolf 2019-07-03 12:30:37 +02:00 • committed by GitHub
commit e38b2ac648
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3 changed files with 26 additions and 82 deletions
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95
frontends/verilog/verilog_parser.y
View file

@ -1021,13 +1021,8 @@ list_of_specparam_assignments:
specparam_assignment: specparam_assignment:
ignspec_id '=' constant_mintypmax_expression ; ignspec_id '=' constant_mintypmax_expression ;
/* ignspec_opt_cond:
pulsestyle_declaration : TOK_IF '(' ignspec_expr ')' | /* empty */;
;
showcancelled_declaration :
;
*/
path_declaration : path_declaration :
simple_path_declaration ';' simple_path_declaration ';'
@ -1036,8 +1031,8 @@ path_declaration :
; ;
simple_path_declaration : simple_path_declaration :
parallel_path_description '=' path_delay_value | ignspec_opt_cond parallel_path_description '=' path_delay_value |
full_path_description '=' path_delay_value ignspec_opt_cond full_path_description '=' path_delay_value
; ;
path_delay_value : path_delay_value :
@ -1047,32 +1042,20 @@ path_delay_value :
; ;
list_of_path_delay_extra_expressions : list_of_path_delay_extra_expressions :
/* ',' path_delay_expression | ',' path_delay_expression list_of_path_delay_extra_expressions;
t_path_delay_expression
| trise_path_delay_expression ',' tfall_path_delay_expression specify_edge_identifier :
| trise_path_delay_expression ',' tfall_path_delay_expression ',' tz_path_delay_expression TOK_POSEDGE | TOK_NEGEDGE ;
| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression
| t01_path_delay_expression ',' t10_path_delay_expression ',' t0z_path_delay_expression ','
tz1_path_delay_expression ',' t1z_path_delay_expression ',' tz0_path_delay_expression ','
t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
*/
',' path_delay_expression
| ',' path_delay_expression ',' path_delay_expression
| ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression
| ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression
;
parallel_path_description : parallel_path_description :
'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' |
'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor opt_polarity_operator ':' ignspec_expr ')' ')' |
'(' specify_edge_identifier specify_input_terminal_descriptor '=' '>' '(' specify_output_terminal_descriptor TOK_POS_INDEXED ignspec_expr ')' ')' ;
full_path_description : full_path_description :
'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ; '(' list_of_path_inputs '*' '>' list_of_path_outputs ')' |
'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs opt_polarity_operator ':' ignspec_expr ')' ')' |
'(' specify_edge_identifier list_of_path_inputs '*' '>' '(' list_of_path_outputs TOK_POS_INDEXED ignspec_expr ')' ')' ;
// This was broken into 2 rules to solve shift/reduce conflicts // This was broken into 2 rules to solve shift/reduce conflicts
list_of_path_inputs : list_of_path_inputs :
@ -1112,56 +1095,6 @@ system_timing_args :
system_timing_arg | system_timing_arg |
system_timing_args ',' system_timing_arg ; system_timing_args ',' system_timing_arg ;
/*
t_path_delay_expression :
path_delay_expression;
trise_path_delay_expression :
path_delay_expression;
tfall_path_delay_expression :
path_delay_expression;
tz_path_delay_expression :
path_delay_expression;
t01_path_delay_expression :
path_delay_expression;
t10_path_delay_expression :
path_delay_expression;
t0z_path_delay_expression :
path_delay_expression;
tz1_path_delay_expression :
path_delay_expression;
t1z_path_delay_expression :
path_delay_expression;
tz0_path_delay_expression :
path_delay_expression;
t0x_path_delay_expression :
path_delay_expression;
tx1_path_delay_expression :
path_delay_expression;
t1x_path_delay_expression :
path_delay_expression;
tx0_path_delay_expression :
path_delay_expression;
txz_path_delay_expression :
path_delay_expression;
tzx_path_delay_expression :
path_delay_expression;
*/
path_delay_expression : path_delay_expression :
ignspec_constant_expression; ignspec_constant_expression;

11
tests/various/specify.v
View file

@ -7,9 +7,11 @@ module test (
if (EN) Q <= D; if (EN) Q <= D;
specify specify
if (EN) (CLK *> (Q : D)) = (1, 2:3:4); `ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS
if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4);
$setup(D, posedge CLK &&& EN, 5); $setup(D, posedge CLK &&& EN, 5);
$hold(posedge CLK, D &&& EN, 6); $hold(posedge CLK, D &&& EN, 6);
`endif
endspecify endspecify
endmodule endmodule
@ -28,3 +30,10 @@ module test2 (
(B => Q) = 1.5; (B => Q) = 1.5;
endspecify endspecify
endmodule endmodule
module issue01144(input clk, d, output q);
specify
(posedge clk => (q +: d)) = (3,1);
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule

2
tests/various/specify.ys
View file

@ -54,3 +54,5 @@ equiv_struct
equiv_induct -seq 5 equiv_induct -seq 5
equiv_status -assert equiv_status -assert
design -reset design -reset
read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v