mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-12 20:18:20 +00:00
abc9_ops: -prep_dff_map to warn if no specify cells
This commit is contained in:
parent
23c53a6bdd
commit
e38b1280f9
|
@ -206,13 +206,18 @@ void prep_dff_map(RTLIL::Design *design)
|
||||||
D = w;
|
D = w;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
|
if (GetSize(specify_cells) == 0) {
|
||||||
// to $_DFF_[NP]_.D since it will be moved into
|
log_warning("Module '%s' marked (* abc9_flop *) contains no specify timing information.\n", log_id(module));
|
||||||
// the submodule
|
}
|
||||||
for (auto cell : specify_cells) {
|
else {
|
||||||
auto DST = cell->getPort(ID::DST);
|
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
|
||||||
DST.replace(Q, D);
|
// to $_DFF_[NP]_.D since it will be moved into
|
||||||
cell->setPort(ID::DST, DST);
|
// the submodule
|
||||||
|
for (auto cell : specify_cells) {
|
||||||
|
auto DST = cell->getPort(ID::DST);
|
||||||
|
DST.replace(Q, D);
|
||||||
|
cell->setPort(ID::DST, DST);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
continue_outer_loop: ;
|
continue_outer_loop: ;
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in a new issue