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	xaiger: no longer use nonstandard even/odd to designate +ve/-ve polarity
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					 1 changed files with 5 additions and 16 deletions
				
			
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			@ -620,27 +620,16 @@ struct XAigerWriter
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			auto write_s_buffer = std::bind(write_buffer, std::ref(s_buffer), std::placeholders::_1);
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			write_s_buffer(ff_bits.size());
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			dict<SigBit, int> clk_to_mergeability;
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			for (const auto &i : ff_bits) {
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				const Cell *cell = i.second;
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				log_assert(cell->type.in(ID($_DFF_N_), ID($_DFF_P_)));
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				SigBit clock = sigmap(cell->getPort(ID::C));
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				clk_to_mergeability.insert(std::make_pair(clock, clk_to_mergeability.size()*2+1));
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			}
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			dict<SigSpec, int> clk_to_mergeability;
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			for (const auto &i : ff_bits) {
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				const SigBit &d = i.first;
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				const Cell *cell = i.second;
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				SigBit clock = sigmap(cell->getPort(ID::C));
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				int mergeability = clk_to_mergeability.at(clock);
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				SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
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				auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
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				int mergeability = r.first->second;
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				log_assert(mergeability > 0);
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				if (cell->type == ID($_DFF_N_))
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					write_r_buffer(mergeability);
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				else if (cell->type == ID($_DFF_P_))
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					write_r_buffer(mergeability+1);
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				else log_abort();
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				write_r_buffer(mergeability);
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				SigBit Q = sigmap(cell->getPort(ID::Q));
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				State init = init_map.at(Q, State::Sx);
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