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Added init= attribute for fpga-style reset values

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Clifford Wolf 2013-11-20 01:49:37 +01:00
parent a1353ec61b
commit e340532ce5
2 changed files with 23 additions and 6 deletions
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4
README
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@ -258,6 +258,10 @@ Verilog Attributes and non-standard features
never be removed by the optimizer. This is used for example for cells that never be removed by the optimizer. This is used for example for cells that
have hidden connections that are not part of the netlist, such as IO pads. have hidden connections that are not part of the netlist, such as IO pads.
- The "init" attribute on wires is set by the frontend when a register is
initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
to add the necessary reset logic.
- In addition to the (* ... *) attribute syntax, yosys supports - In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset for everything that comes after the {* ... *} statement. (Reset

25
frontends/verilog/parser.y
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@ -246,8 +246,22 @@ module_args:
optional_comma: optional_comma:
',' | /* empty */; ',' | /* empty */;
module_arg_opt_assignment:
'=' expr {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
if (!ast_stack.back()->children.back()->is_reg) {
AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str;
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
} else
ast_stack.back()->children.back()->attributes["\\init"] = $2;
} else
frontend_verilog_yyerror("Syntax error.");
} |
/* empty */;
module_arg: module_arg:
TOK_ID range { TOK_ID {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
AstNode *node = ast_stack.back()->children.back()->clone(); AstNode *node = ast_stack.back()->children.back()->clone();
node->str = *$1; node->str = *$1;
@ -258,10 +272,8 @@ module_arg:
frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str()); frontend_verilog_yyerror("Duplicate module port `%s'.", $1->c_str());
port_stubs[*$1] = ++port_counter; port_stubs[*$1] = ++port_counter;
} }
if ($2 != NULL)
delete $2;
delete $1; delete $1;
} | } module_arg_opt_assignment |
attr wire_type range TOK_ID { attr wire_type range TOK_ID {
AstNode *node = $2; AstNode *node = $2;
node->str = *$4; node->str = *$4;
@ -275,7 +287,7 @@ module_arg:
ast_stack.back()->children.push_back(node); ast_stack.back()->children.push_back(node);
append_attr(node, $1); append_attr(node, $1);
delete $4; delete $4;
}; } module_arg_opt_assignment;
wire_type: wire_type:
{ {
@ -501,7 +513,8 @@ wire_name_and_opt_assign:
AstNode *wire = new AstNode(AST_IDENTIFIER); AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str; wire->str = ast_stack.back()->children.back()->str;
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $3));
} } else
ast_stack.back()->children.back()->attributes["\\init"] = $3;
}; };
wire_name: wire_name: