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annotate_ff_width pass

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Stan Lee 2026-06-01 16:35:30 -07:00
parent d1ec970f86
commit e3134c6692
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1
passes/silimate/Makefile.inc
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@ -1,6 +1,7 @@
OBJS += passes/silimate/activity.o
OBJS += passes/silimate/annotate_cell_fanout.o
OBJS += passes/silimate/annotate_ff_width.o
OBJS += passes/silimate/breakreduce.o
OBJS += passes/silimate/breaksop.o
OBJS += passes/silimate/bus_rebuild.o

63
passes/silimate/annotate_ff_width.cc Normal file
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/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2026 Stan Lee <stan@silimate.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct AnnotateFfWidthPass : public Pass {
AnnotateFfWidthPass() : Pass("annotate_ff_width", "annotate every flip-flop with its bit-width") { }
void help() override
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" annotate_ff_width [selection]\n");
log("\n");
log("Annotate every flip-flop with its width.");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
log_header(design, "Executing ANNOTATE_FF_WIDTH pass.\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
break;
extra_args(args, argidx, design);
// Loop through all flip-flops and annotate with their width
int annotated = 0;
for (auto module : design->selected_modules()) {
for (auto cell : module->selected_cells()) {
if (!cell->is_builtin_ff())
continue;
int width;
if (cell->hasParam(ID::WIDTH))
width = cell->getParam(ID::WIDTH).as_int();
else if (cell->hasPort(ID::Q))
width = GetSize(cell->getPort(ID::Q));
else
width = 1;
cell->set_string_attribute(ID(ff_width), std::to_string(width));
annotated++;
}
}
log("Annotated %d flip-flop / latch cells.\n", annotated);
}
} AnnotateFfWidthPass;
PRIVATE_NAMESPACE_END