mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-02 04:11:22 +00:00
Code Activity

Add SB_CARRY to ice40_opt test

Browse source
This commit is contained in:
Eddie Hung 2019-08-28 18:44:57 -07:00
parent dd42aa87b9
commit e301a3dadb
1 changed files with 5 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

8
tests/ice40/ice40_opt.ys
View file

@ -1,5 +1,5 @@
read_verilog -icells -formal <<EOT read_verilog -icells -formal <<EOT
module top(input CI, I0, output CO, O); module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0; wire A = 1'b0, B = 1'b0;
\$__ICE40_CARRY_WRAPPER #( \$__ICE40_CARRY_WRAPPER #(
// A[0]: 1010 1010 1010 1010 // A[0]: 1010 1010 1010 1010
@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O);
// A[2]: 1111 0000 1111 0000 // A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000 // A[3]: 1111 1111 0000 0000
.LUT(~16'b 0110_1001_1001_0110) .LUT(~16'b 0110_1001_1001_0110)
) fadd ( ) u0 (
.A(A), .A(A),
.B(B), .B(B),
.CI(CI), .CI(CI),
.I0(I0), .I0(I0),
.I3(CI), .I3(CI),
.CO(CO), .CO(CO[0]),
.O(O) .O(O)
); );
SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
endmodule endmodule
EOT EOT
equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:$lut select -assert-count 1 t:$lut