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https://github.com/YosysHQ/yosys
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Reduce amount of trailing whitespace in code base
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68a6937173
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9 changed files with 29 additions and 29 deletions
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@ -32,7 +32,7 @@ module fa
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wire VCC;
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assign VCC = 1'b1;
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cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
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.dataa(a_c),
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.datab(b_c),
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@ -40,7 +40,7 @@ module fa
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.datad(VCC));
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defparam syn__05_.lut_mask = 16'b1001011010010110;
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defparam syn__05_.sum_lutc_input = "datac";
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cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
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.dataa(cin_c),
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.datab(b_c),
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@ -48,11 +48,11 @@ module fa
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.datad(VCC));
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defparam syn__06_.lut_mask = 16'b1110000011100000;
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defparam syn__06_.sum_lutc_input = "datac";
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endmodule // fa
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module f_stage();
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endmodule // f_stage
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module f_end();
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@ -88,7 +88,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
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.cin_c(C[0]),
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.cout_t(C0[1]),
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.sum_x(Y[0]));
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genvar i;
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generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
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cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
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@ -76,7 +76,7 @@ module \$lut (A, Y);
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wire VCC;
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wire GND;
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assign {VCC,GND} = {1'b1,1'b0};
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generate
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if (WIDTH == 1) begin
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assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
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@ -151,7 +151,7 @@ module \$lut (A, Y);
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TODO: There's not a just 7-input function on Cyclone V, see the following note:
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**Extended LUT Mode**
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Use extended LUT mode to implement a specific set of 7-input functions. The set must
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be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
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be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
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[source](Device Interfaces and Integration Basics for Cyclone V Devices).
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end*/
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else
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