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Some tidy up

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Krystine Sherwin 2023-08-14 12:13:29 +12:00
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docs/source/yosys_internals/flow/verilog_frontend.rst
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@ -409,7 +409,9 @@ multiplexers.
In more complex examples (e.g. asynchronous resets) the part of the
``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the asynchronous
reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This
is done by the :cmd:ref:`proc_adff` pass.
is done by the ``proc_adff`` pass.
.. todo:: The ``proc_adff`` pass doesn't exist anymore?
The ProcessGenerator algorithm
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~