Some tidy up

docs/source/yosys_internals/flow/index.rst

@@ -12,7 +12,7 @@ This scripts contain three types of commands:
   available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .).
 
 .. toctree:: 
-	:maxdepth: 2
+	:maxdepth: 3
 
 	overview
 	control_and_data

docs/source/yosys_internals/flow/verilog_frontend.rst

@@ -409,7 +409,9 @@ multiplexers.
 In more complex examples (e.g. asynchronous resets) the part of the
 ``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the asynchronous
 reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This
-is done by the :cmd:ref:`proc_adff` pass.
+is done by the ``proc_adff`` pass.
+
+.. todo:: The ``proc_adff`` pass doesn't exist anymore?
 
 The ProcessGenerator algorithm
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

docs/source/yosys_internals/formats/index.rst

@@ -2,7 +2,7 @@ Internal formats
 ================
 
 .. toctree:: 
-	:maxdepth: 2
+	:maxdepth: 3
 
 	overview
 	rtlil_rep

docs/source/yosys_internals/formats/rtlil_rep.rst

@@ -78,9 +78,9 @@ This has three advantages:
 
 -  Second, the information about which identifiers were originally provided by
    the user is always available which can help guide some optimizations. For
-   example the :cmd:ref:`opt_rmunused` tries to preserve signals with a
-   user-provided name but doesn't hesitate to delete signals that have
-   auto-generated names when they just duplicate other signals.
+   example the ``opt_rmunused`` tries to preserve signals with a user-provided
+   name but doesn't hesitate to delete signals that have auto-generated names
+   when they just duplicate other signals.
 
 -  Third, the delicate job of finding suitable auto-generated public visible
    names is deferred to one central location. Internally auto-generated names

docs/source/yosys_internals/index.rst

@@ -23,7 +23,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the
 
 .. _k68 CPU: http://opencores.org/projects/k68
 
-As of this writing a Yosys VHDL frontend is in development.
+As of this writing, a Yosys VHDL frontend is in development.
 
 Yosys is written in C++ (using some features from the new C++11 standard). This
 chapter describes some of the fundamental Yosys data structures. For the sake of
@@ -31,11 +31,10 @@ simplicity the C++ type names used in the Yosys implementation are used in this
 chapter, even though the chapter only explains the conceptual idea behind it and
 can be used as reference to implement a similar system in any language.
 
-.. toctree:: 
+.. toctree::
+	:maxdepth: 3
 
 	flow/index
 	formats/index
 	techmap
 	extensions
-
-.. todo:: copypaste