mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-28 03:15:50 +00:00
Code Activity

Some tidy up

Browse source
This commit is contained in:
Krystine Sherwin 2023-08-14 12:13:29 +12:00
parent 685da6a2e5
commit e2c0f8fc50
No known key found for this signature in database
10 changed files with 28 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

8
docs/source/appendix/APPNOTE_011_Design_Investigation.rst
View file

@ -78,10 +78,10 @@ A simple circuit
:numref:`example_src` shows a simple synthesis script and a Verilog file that
demonstrate the usage of show in a simple setting. Note that :cmd:ref:`show` is
called with the :cmd:ref:`-pause` option, that halts execution of the Yosys
script until the user presses the Enter key. The ``show -pause`` command also
allows the user to enter an interactive shell to further investigate the circuit
before continuing synthesis.
called with the ``-pause`` option, that halts execution of the Yosys script
until the user presses the Enter key. The ``show -pause`` command also allows
the user to enter an interactive shell to further investigate the circuit before
continuing synthesis.
So this script, when executed, will show the design after each of the three
synthesis commands. The generated circuit diagrams are shown in