From e273ed52758599cb156cf3c309905da70826fe2d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 20 Aug 2019 15:09:38 -0700
Subject: [PATCH] Wrap SRL{16,32} too
---
techlibs/xilinx/abc_map.v | 38 ++++++++++++++++++++++++++++++++++++-
techlibs/xilinx/abc_model.v | 32 +++++++++++++++++++++++++------
techlibs/xilinx/abc_unmap.v | 37 +++++++++++++++++++++++++++++++++++-
3 files changed, 99 insertions(+), 8 deletions(-)
diff --git a/techlibs/xilinx/abc_map.v b/techlibs/xilinx/abc_map.v
index 0d69e8c08..56b4fe7f9 100644
--- a/techlibs/xilinx/abc_map.v
+++ b/techlibs/xilinx/abc_map.v
@@ -185,5 +185,41 @@ module \$__ABC_RAM128X1D (
);
\$__ABC_LUTMUX7 dpo (.A(\$DPO ), .S(A), .Y(DPO));
\$__ABC_LUTMUX7 spo (.A(\$SPO ), .S(A), .Y(SPO));
-
+endmodule
+
+module SRL16E (
+ output Q,
+ input A0, A1, A2, A3, CE, CLK, D
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ wire \$Q ;
+ \$__ABC_SRL16E #(
+ .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .Q(\$Q ),
+ .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+ );
+ // TODO: Check if SRL uses fast inputs or slow inputs
+ \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A0, A1, A2, A3, 1'b0, 1'b0}), .Y(Q));
+endmodule
+
+module SRLC32E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *) output Q,
+ (* abc_arrival=1114 *) output Q31,
+ input [4:0] A,
+ input CE, CLK, D
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ wire \$Q ;
+ \$__ABC_SRLC32E #(
+ .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .Q(\$Q ), .Q31(Q31),
+ .A(A), .CE(CE), .CLK(CLK), .D(D)
+ );
+ // TODO: Check if SRL uses fast inputs or slow inputs
+ \$__ABC_LUTMUX6 q (.A(\$Q ), .S({A, 1'b0}), .Y(Q));
endmodule
diff --git a/techlibs/xilinx/abc_model.v b/techlibs/xilinx/abc_model.v
index 76ef41a91..7162bd213 100644
--- a/techlibs/xilinx/abc_model.v
+++ b/techlibs/xilinx/abc_model.v
@@ -123,8 +123,8 @@ endmodule
module \$__ABC_RAM32X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@@ -134,8 +134,8 @@ module \$__ABC_RAM32X1D (
endmodule
module \$__ABC_RAM64X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@@ -147,8 +147,8 @@ module \$__ABC_RAM64X1D (
endmodule
module \$__ABC_RAM128X1D (
- // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
- (* abc_arrival=1472 *) output DPO, SPO,
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc_arrival=1153 *) output DPO, SPO,
input D,
input WCLK,
input WE,
@@ -157,3 +157,23 @@ module \$__ABC_RAM128X1D (
parameter INIT = 128'h0;
parameter IS_WCLK_INVERTED = 1'b0;
endmodule
+
+module SRL16E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *) output Q,
+ input A0, A1, A2, A3, CE, CLK, D
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+endmodule
+
+module SRLC32E (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
+ (* abc_arrival=1472 *) output Q,
+ (* abc_arrival=1114 *) output Q31,
+ input [4:0] A,
+ input CE, CLK, D
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+endmodule
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v
index f2708b477..d00d27e2e 100644
--- a/techlibs/xilinx/abc_unmap.v
+++ b/techlibs/xilinx/abc_unmap.v
@@ -139,7 +139,10 @@ module \$__ABC_FDPE_1 (output Q,
);
endmodule
-module \$__ABC_LUTMUX (input A, input [5:0] S, output Y);
+module \$__ABC_LUTMUX6 (input A, input [5:0] S, output Y);
+ assign Y = A;
+endmodule
+module \$__ABC_LUTMUX7 (input A, input [6:0] S, output Y);
assign Y = A;
endmodule
@@ -202,3 +205,35 @@ module \$__ABC_RAM128X1D (
.DPRA(DPRA)
);
endmodule
+
+module \$__ABC_SRL16E (
+ output Q,
+ input A0, A1, A2, A3, CE, CLK, D
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+ SRL16E #(
+ .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .Q(Q),
+ .A0(A0), .A1(A1), .A2(A2), .A3(A3), .CE(CE), .CLK(CLK), .D(D)
+ );
+endmodule
+
+module \$__ABC_SRLC32E (
+ output Q,
+ output Q31,
+ input [4:0] A,
+ input CE, CLK, D
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+
+ SRLC32E #(
+ .INIT(INIT), .IS_CLK_INVERTED(IS_CLK_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .Q(Q), .Q31(Q31),
+ .A(A), .CE(CE), .CLK(CLK), .D(D)
+ );
+endmodule