From e2627b367e5694003a23a15a30589be8ce00319a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 5 Jun 2026 21:50:04 +0200 Subject: [PATCH] rtlil: set Module::design before name at all construction sites --- frontends/aiger/aigerparse.cc | 1 + frontends/ast/ast.cc | 1 + frontends/blif/blifparse.cc | 1 + frontends/json/jsonparse.cc | 1 + frontends/liberty/liberty.cc | 1 + frontends/rtlil/rtlil_frontend.cc | 1 + frontends/verific/verific.cc | 1 + passes/hierarchy/hierarchy.cc | 1 + passes/hierarchy/submod.cc | 1 + passes/sat/miter.cc | 1 + passes/techmap/extract.cc | 1 + 11 files changed, 11 insertions(+) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 1fa657e5c..009e1e81c 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -222,6 +222,7 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString : design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports), aiger_autoidx(autoidx++) { module = new RTLIL::Module; + module->design = design; module->name = module_name; if (design->module(module->name)) log_error("Duplicate definition of module %s!\n", module->name.unescape()); diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index fe1bc4659..9b12e9ca7 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1953,6 +1953,7 @@ RTLIL::Module *AstModule::clone() const RTLIL::Module *AstModule::clone(RTLIL::Design *dst, bool src_id_verbatim) const { AstModule *new_mod = new AstModule; + new_mod->design = dst; new_mod->name = name; dst->add(new_mod); cloneInto(new_mod, src_id_verbatim); diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 2eae64fa1..6b67bb99c 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -167,6 +167,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (module != nullptr) goto error; module = new RTLIL::Module; + module->design = design; lastcell = nullptr; char *name = strtok(NULL, " \t\r\n"); if (name == nullptr) diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 4354f0730..c5ba389ad 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -311,6 +311,7 @@ void json_import(Design *design, string &modname, JsonNode *node) log("Importing module %s from JSON tree.\n", modname); Module *module = new RTLIL::Module; + module->design = design; module->name = RTLIL::escape_id(modname.c_str()); if (design->module(module->name)) diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 447f438a8..ff63f7f8f 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -606,6 +606,7 @@ struct LibertyFrontend : public Frontend { parse_type_map(type_map, cell); RTLIL::Module *module = new RTLIL::Module; + module->design = design; std::string cell_name = RTLIL::escape_id(cell->args.at(0)); module->name = cell_name; diff --git a/frontends/rtlil/rtlil_frontend.cc b/frontends/rtlil/rtlil_frontend.cc index 745f00935..fe69f6de0 100644 --- a/frontends/rtlil/rtlil_frontend.cc +++ b/frontends/rtlil/rtlil_frontend.cc @@ -444,6 +444,7 @@ struct RTLILFrontendWorker { } current_module = new RTLIL::Module; + current_module->design = design; current_module->name = std::move(module_name); if (delete_current_module) { // Module is about to be discarded — drop its src attribute diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f7450d9b9..7233d165c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1492,6 +1492,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma } module = new RTLIL::Module; + module->design = design; module->name = module_name; design->add(module); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 4b8830dbd..728bdf485 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -119,6 +119,7 @@ void generate(RTLIL::Design *design, const std::vector &celltypes, log_assert(indices.empty()); RTLIL::Module *mod = new RTLIL::Module; + mod->design = design; mod->name = celltype; mod->attributes[ID::blackbox] = RTLIL::Const(1); design->add(mod); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index bf135386c..885af5388 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -116,6 +116,7 @@ struct SubmodWorker } RTLIL::Module *new_mod = new RTLIL::Module; + new_mod->design = design; new_mod->name = submod.full_name; design->add(new_mod); int auto_name_counter = 1; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 5dd1b07b4..411032f56 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -131,6 +131,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", miter_name.unescape(), gold_name.unescape(), gate_name.unescape()); RTLIL::Module *miter_module = new RTLIL::Module; + miter_module->design = design; miter_module->name = miter_name; design->add(miter_module); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 466bef68a..d920289d9 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -716,6 +716,7 @@ struct ExtractPass : public Pass { } RTLIL::Module *newMod = new RTLIL::Module; + newMod->design = map; newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, haystack_map.at(result.graphId)->name.unescape(), result.totalMatchesAfterLimits); map->add(newMod);