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https://github.com/YosysHQ/yosys
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icell_liberty: flop harder
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parent
fd344e4611
commit
e2484779e7
1 changed files with 24 additions and 27 deletions
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@ -1,21 +1,3 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Martin Povišer <povik@cutebit.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/ff.h"
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@ -32,12 +14,12 @@ struct LibertyStubber {
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void liberty_prefix(std::ostream& f)
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{
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f << "/*\n";
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f << stringf("Models interfaces of select Yosys internal cell.\n");
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f << stringf("Likely contains INCORRECT POLARITIES.\n");
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f << stringf("Impractical for any simulation, synthesis, or timing.\n");
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f << stringf("Intended purely for SDC expansion.\n");
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f << stringf("Do not microwave or tumble dry.\n");
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f << stringf("Generated by %s\n", yosys_maybe_version());
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f << stringf("\tModels interfaces of select Yosys internal cell.\n");
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f << stringf("\tLikely contains INCORRECT POLARITIES.\n");
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f << stringf("\tImpractical for any simulation, synthesis, or timing.\n");
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f << stringf("\tIntended purely for SDC expansion.\n");
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f << stringf("\tDo not microwave or tumble dry.\n");
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f << stringf("\tGenerated by %s\n", yosys_maybe_version());
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f << "*/\n";
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f << "library (yosys) {\n";
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f << "\tinput_threshold_pct_fall : 50;\n";
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@ -82,7 +64,13 @@ struct LibertyStubber {
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f << "\tcell (\"" << derived_name << "\") {\n";
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auto& base_type = ct.cell_types[base_name];
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i.indent = 3;
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for (auto x : derived->ports) {
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auto sorted_ports = derived->ports;
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// Hack for CLK and C coming before Q does
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auto cmp = [](IdString l, IdString r) { return l.str() < r.str(); };
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std::sort(sorted_ports.begin(), sorted_ports.end(), cmp);
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std::string clock_pin_name = "";
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for (auto x : sorted_ports) {
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std::string port_name = RTLIL::unescape_id(x);
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bool is_input = base_type.inputs.count(x);
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bool is_output = base_type.outputs.count(x);
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f << "\t\tpin (" << RTLIL::unescape_id(x.str()) << ") {\n";
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@ -93,10 +81,19 @@ struct LibertyStubber {
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} else {
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i.item("direction", "inout");
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}
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if (RTLIL::unescape_id(x) == "CLK" || RTLIL::unescape_id(x) == "C")
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if (port_name == "CLK" || port_name == "C") {
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i.item("clock", "true");
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if (RTLIL::unescape_id(x) == "Q")
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clock_pin_name = port_name;
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}
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if (port_name == "Q") {
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i.item("function", "IQ");
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f << "\t\t\ttiming () {\n";
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i.indent++;
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log_assert(clock_pin_name.size());
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i.item("related_pin", clock_pin_name);
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i.indent--;
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f << "\t\t\t}\n";
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}
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f << "\t\t}\n";
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}
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