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Progress on AppNote 011

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Clifford Wolf 2013-11-29 12:51:16 +01:00
parent 1b3a60976d
commit e23a0072ec
6 changed files with 190 additions and 11 deletions
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9
manual/APPNOTE_011_Design_Investigation/example.v
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@ -1,5 +1,6 @@
module example(input clk, a, b, c, output reg [1:0] y);
always @(posedge clk)
if (c)
y <= c ? a + b : 2'd0;
module example(input clk, a, b, c,
output reg [1:0] y);
always @(posedge clk)
if (c)
y <= c ? a + b : 2'd0;
endmodule