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Eddie Hung 2019-09-13 09:34:40 -07:00
parent 734034a872
commit e235dd0785
1 changed files with 14 additions and 12 deletions
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14
techlibs/xilinx/abc_model.v
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@ -52,10 +52,12 @@ endmodule
// path between AREG/BREG/CREG/etc. and P/PCOUT. // path between AREG/BREG/CREG/etc. and P/PCOUT.
// Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at // Since the Aq/ADq/Bq/etc. inputs are assumed to arrive at
// the box at zero time, the combinatorial delay through // the box at zero time, the combinatorial delay through
// these muxes thus represents the clock-to-q delay at // these boxes thus represents the clock-to-q delay
// P/PCOUT. // (arrival time) at P/PCOUT.
// Doing so should means that ABC is able to analyse the // Doing so should means that ABC is able to analyse the
// worst-case delay through to P. // worst-case delay through to P, regardless of if it was
// through any combinatorial paths (e.g. B, below) or an
// internal register (A2REG).
// However, the true value of being as complete as this is // However, the true value of being as complete as this is
// questionable since if AREG=1 and BREG=0 (as below) // questionable since if AREG=1 and BREG=0 (as below)
// then the worse-case path would very likely be through B // then the worse-case path would very likely be through B
@ -67,10 +69,10 @@ endmodule
// for AREG.Q | // for AREG.Q |
// | // |
// +---------+ | __ // +---------+ | __
// A --X X-| | +--| \ // A >>--X X-| | +--| \
// | DSP48E1 |P | |--- P // | DSP48E1 |P | |--->> P
// | AREG=1 |-------|__/ // | AREG=1 |-------|__/
// B ------| | // B >>------| |
// +---------+ // +---------+
// //
(* abc_box_id=2100 *) (* abc_box_id=2100 *)