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synth_quicklogic: rearrange files to prepare for adding more architectures

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N. Engelhardt 2023-07-07 15:27:21 +02:00 • committed by Martin Povišer
parent 031ad38b5c
commit e230a871be
20 changed files with 139 additions and 113 deletions
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11
techlibs/quicklogic/pp3/latches_map.v Normal file
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@ -0,0 +1,11 @@
module \$_DLATCH_P_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = E ? D : Q;
endmodule
module \$_DLATCH_N_ (E, D, Q);
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
input E, D;
output Q = !E ? D : Q;
endmodule