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synth_quicklogic: rearrange files to prepare for adding more architectures

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N. Engelhardt 2023-07-07 15:27:21 +02:00 • committed by Martin Povišer
parent 031ad38b5c
commit e230a871be
20 changed files with 139 additions and 113 deletions
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4
techlibs/quicklogic/pp3/ffs_map.v Normal file
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module \$_DFFSRE_PPPP_ (input C, S, R, E, D, output Q);
wire _TECHMAP_REMOVEINIT_Q_ = 1;
dffepc #(.INIT(1'b0)) _TECHMAP_REPLACE_ (.CLK(C), .PRE(S), .CLR(R), .EN(E), .D(D), .Q(Q));
endmodule