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synth_quicklogic: rearrange files to prepare for adding more architectures

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N. Engelhardt 2023-07-07 15:27:21 +02:00 • committed by Martin Povišer
parent 031ad38b5c
commit e230a871be
20 changed files with 139 additions and 113 deletions
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36
techlibs/quicklogic/pp3/cells_map.v Normal file
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@ -0,0 +1,36 @@
module \$_MUX8_ (
A, B, C, D, E, F, G, H, S, T, U, Y
);
input A, B, C, D, E, F, G, H, S, T, U;
output Y;
mux8x0 _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.H(H),
.S0(S),
.S1(T),
.S2(U),
.Q(Y)
);
endmodule
module \$_MUX4_ (
A, B, C, D, S, T, U, Y
);
input A, B, C, D, S, T, U;
output Y;
mux4x0 _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.C(C),
.D(D),
.S0(S),
.S1(T),
.Q(Y)
);
endmodule