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abc9_ops: ignore (* abc9_flop *) if not '-dff'
This commit is contained in:
Eddie Hung
parent
a76520112d
commit
e22fee6cdd
4 changed files with 120 additions and 110 deletions
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@ -192,7 +192,7 @@ struct Abc9Pass : public ScriptPass
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cleanup = true;
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lut_mode = false;
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maxlut = 0;
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box_file = "(null)";
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box_file = "";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -286,9 +286,9 @@ struct Abc9Pass : public ScriptPass
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else if (!lut_mode)
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run(stringf("abc9_ops -prep_lut %d", maxlut));
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if (help_mode)
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run("abc9_ops -prep_box [<-box>|(null)]");
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else
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run(stringf("abc9_ops -prep_box %s", box_file.c_str()));
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run("abc9_ops -prep_box [-dff]", "(skip if -box)");
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else if (box_file.empty())
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run(stringf("abc9_ops -prep_box %s", dff_mode ? "-dff" : ""));
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run("select -set abc9_holes A:abc9_holes");
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run("flatten -wb @abc9_holes");
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run("techmap @abc9_holes");
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@ -378,7 +378,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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}
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}
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void prep_delays(RTLIL::Design *design)
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void prep_delays(RTLIL::Design *design, bool dff_mode)
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{
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// Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes
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// (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations
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@ -407,7 +407,7 @@ void prep_delays(RTLIL::Design *design)
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log_assert(inst_module);
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blackboxes.insert(inst_module);
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if (inst_module->get_bool_attribute(ID(abc9_flop))) {
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if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
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flops.insert(inst_module);
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continue; // do not add $__ABC9_DELAY boxes to flops
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// as delays will be captured in the flop box
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@ -474,10 +474,8 @@ void prep_delays(RTLIL::Design *design)
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continue;
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ports.clear();
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for (const auto &i : arrivals) {
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log_dump(i.first, i.first.wire->name);
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for (const auto &i : arrivals)
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ports.insert(i.first.wire);
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}
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for (auto wire : ports) {
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log_assert(wire->port_output);
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ss.str("");
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@ -537,7 +535,7 @@ void prep_delays(RTLIL::Design *design)
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inst_module = design->module(derived_type);
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log_assert(inst_module);
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auto &cell_requireds = requireds_cache[cell->type];
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auto &cell_requireds = requireds_cache[derived_type];
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for (auto &conn : cell->connections_) {
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auto port_wire = inst_module->wire(conn.first);
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if (!port_wire->port_input)
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@ -569,7 +567,7 @@ void prep_delays(RTLIL::Design *design)
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#ifndef NDEBUG
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if (ys_debug(1)) {
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static std::set<std::pair<IdString,IdString>> seen;
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if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
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if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]);
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}
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#endif
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auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
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@ -652,64 +650,66 @@ void write_lut(RTLIL::Module *module, const std::string &dst) {
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ofs.close();
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}
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void prep_box(RTLIL::Design *design)
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void prep_box(RTLIL::Design *design, bool dff_mode)
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{
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std::stringstream ss;
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int abc9_box_id = 1;
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dict<IdString,std::vector<IdString>> box_ports;
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for (auto module : design->modules()) {
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if (module->get_bool_attribute(ID(abc9_flop))) {
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int num_inputs = 0, num_outputs = 0;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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log_assert(GetSize(wire) == 1);
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if (wire->port_input) num_inputs++;
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if (wire->port_output) num_outputs++;
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auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
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if (abc9_flop) {
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if (dff_mode) {
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int num_inputs = 0, num_outputs = 0;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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log_assert(GetSize(wire) == 1);
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if (wire->port_input) num_inputs++;
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if (wire->port_output) num_outputs++;
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}
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log_assert(num_outputs == 1);
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auto r = module->attributes.insert(ID(abc9_box_id));
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if (r.second)
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r.first->second = abc9_box_id++;
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ss << log_id(module) << " " << r.first->second.as_int();
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ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
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ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
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ss << "#";
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bool first = true;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (!wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << log_id(wire);
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}
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ss << " abc9_ff.Q" << std::endl;
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first = true;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (!wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << wire->attributes.at("\\abc9_required", 0).as_int();
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}
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// Last input is 'abc9_ff.Q'
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ss << " 0" << std::endl << std::endl;
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continue;
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}
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log_assert(num_outputs == 1);
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auto r = module->attributes.insert(ID(abc9_box_id));
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if (r.second)
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r.first->second = abc9_box_id++;
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ss << log_id(module) << " " << r.first->second.as_int();
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ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
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ss << " " << num_inputs+1 << " " << num_outputs << std::endl;
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ss << "#";
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bool first = true;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (!wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << log_id(wire);
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}
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ss << " abc9_ff.Q" << std::endl;
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first = true;
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (!wire->port_input)
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continue;
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if (first)
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first = false;
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else
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ss << " ";
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ss << wire->attributes.at("\\abc9_required", 0).as_int();
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}
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// Last input is 'abc9_ff.Q'
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ss << " 0" << std::endl << std::endl;
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continue;
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}
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auto it = module->attributes.find(ID(abc9_box));
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if (it == module->attributes.end())
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continue;
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module->attributes.erase(it);
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else {
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if (!module->attributes.erase(ID(abc9_box)))
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continue;
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}
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log_assert(!module->attributes.count(ID(abc9_box_id)));
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dict<std::pair<SigBit,SigBit>, std::string> table;
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@ -1241,8 +1241,8 @@ struct Abc9OpsPass : public Pass {
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log(" whiteboxes.\n");
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log("\n");
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log(" -dff\n");
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log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n");
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log(" during -prep_xaiger.\n");
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log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n");
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log(" during -prep_{delays,xaiger,box}.\n");
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log("\n");
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log(" -prep_dff\n");
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log(" compute the clock domain and initial value of each flop in the design.\n");
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@ -1345,17 +1345,17 @@ struct Abc9OpsPass : public Pass {
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if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode))
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log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n");
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if (dff_mode && !prep_xaiger_mode)
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log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n");
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if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode)
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log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n");
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if (check_mode)
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check(design);
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if (prep_delays_mode)
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prep_delays(design);
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prep_delays(design, dff_mode);
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if (prep_lut_mode)
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prep_lut(design, maxlut);
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if (prep_box_mode)
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prep_box(design);
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prep_box(design, dff_mode);
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for (auto mod : design->selected_modules()) {
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if (mod->get_bool_attribute("\\abc9_holes"))
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