mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Add "sim -q" option

Browse source 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
This commit is contained in:
Claire Xenia Wolf 2022-03-11 16:26:11 +01:00
parent be32de1caa
commit e21badd4b3
1 changed files with 19 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

27
passes/sat/sim.cc
View file

@ -77,6 +77,7 @@ struct OutputWriter
struct SimShared struct SimShared
{ {
bool debug = false; bool debug = false;
bool verbose = true;
bool hide_internal = true; bool hide_internal = true;
bool writeback = false; bool writeback = false;
bool zinit = false; bool zinit = false;
@ -181,7 +182,7 @@ struct SimInstance
if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) { if ((shared->fst) && !(shared->hide_internal && wire->name[0] == '$')) {
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name)); fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(wire->name));
if (id==0 && wire->name.isPublic()) if (id==0 && wire->name.isPublic())
log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str()); log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(wire->name)).c_str());
fst_handles[wire] = id; fst_handles[wire] = id;
} }
@ -764,7 +765,7 @@ struct SimInstance
IdString name = qsig.as_wire()->name; IdString name = qsig.as_wire()->name;
fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name)); fstHandle id = shared->fst->getHandle(scope + "." + RTLIL::unescape_id(name));
if (id==0 && name.isPublic()) if (id==0 && name.isPublic())
log_warning("Unable to found wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str()); log_warning("Unable to find wire %s in input file.\n", (scope + "." + RTLIL::unescape_id(name)).c_str());
if (id!=0) { if (id!=0) {
Const fst_val = Const::from_string(shared->fst->valueOf(id)); Const fst_val = Const::from_string(shared->fst->valueOf(id));
set_state(qsig, fst_val); set_state(qsig, fst_val);
@ -919,7 +920,7 @@ struct SimWorker : SimShared
if (debug) if (debug)
log("\n===== 0 =====\n"); log("\n===== 0 =====\n");
else else if (verbose)
log("Simulating cycle 0.\n"); log("Simulating cycle 0.\n");
set_inports(reset, State::S1); set_inports(reset, State::S1);
@ -936,7 +937,7 @@ struct SimWorker : SimShared
{ {
if (debug) if (debug)
log("\n===== %d =====\n", 10*cycle + 5); log("\n===== %d =====\n", 10*cycle + 5);
else else if (verbose)
log("Simulating cycle %d.\n", (cycle*2)+1); log("Simulating cycle %d.\n", (cycle*2)+1);
set_inports(clock, State::S0); set_inports(clock, State::S0);
set_inports(clockn, State::S1); set_inports(clockn, State::S1);
@ -946,7 +947,7 @@ struct SimWorker : SimShared
if (debug) if (debug)
log("\n===== %d =====\n", 10*cycle + 10); log("\n===== %d =====\n", 10*cycle + 10);
else else if (verbose)
log("Simulating cycle %d.\n", (cycle*2)+2); log("Simulating cycle %d.\n", (cycle*2)+2);
set_inports(clock, State::S1); set_inports(clock, State::S1);
@ -1063,7 +1064,8 @@ struct SimWorker : SimShared
try { try {
fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) { fst->reconstructAllAtTimes(fst_clock, startCount, stopCount, [&](uint64_t time) {
log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString()); if (verbose)
log("Co-simulating %s %d [%lu%s].\n", (all_samples ? "sample" : "cycle"), cycle, (unsigned long)time, fst->getTimescaleString());
bool did_something = false; bool did_something = false;
for(auto &item : inputs) { for(auto &item : inputs) {
std::string v = fst->valueOf(item.second); std::string v = fst->valueOf(item.second);
@ -1172,7 +1174,8 @@ struct SimWorker : SimShared
state = 3; state = 3;
break; break;
default: default:
log("Simulating cycle %d.\n", cycle); if (verbose)
log("Simulating cycle %d.\n", cycle);
top->setState(inputs, line); top->setState(inputs, line);
if (cycle) { if (cycle) {
set_inports(clock, State::S1); set_inports(clock, State::S1);
@ -1253,7 +1256,8 @@ struct SimWorker : SimShared
curr_cycle = -1; // force detect change curr_cycle = -1; // force detect change
if (curr_cycle != prev_cycle) { if (curr_cycle != prev_cycle) {
log("Simulating cycle %d.\n", cycle); if (verbose)
log("Simulating cycle %d.\n", cycle);
set_inports(clock, State::S1); set_inports(clock, State::S1);
set_inports(clockn, State::S0); set_inports(clockn, State::S0);
update(); update();
@ -1623,6 +1627,9 @@ struct SimPass : public Pass {
log(" -sim-gate\n"); log(" -sim-gate\n");
log(" co-simulation, x in FST can match any value in simulation\n"); log(" co-simulation, x in FST can match any value in simulation\n");
log("\n"); log("\n");
log(" -q\n");
log(" disable per-cycle/sample log message\n");
log("\n");
log(" -d\n"); log(" -d\n");
log(" enable debug output\n"); log(" enable debug output\n");
log("\n"); log("\n");
@ -1695,6 +1702,10 @@ struct SimPass : public Pass {
worker.hide_internal = false; worker.hide_internal = false;
continue; continue;
} }
if (args[argidx] == "-q") {
worker.verbose = false;
continue;
}
if (args[argidx] == "-d") { if (args[argidx] == "-d") {
worker.debug = true; worker.debug = true;
continue; continue;