mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	abc9_ops: -prep_delays to not insert delay box if input connection is const
This commit is contained in:
		
							parent
							
								
									8b5fb99245
								
							
						
					
					
						commit
						e2044fd9c7
					
				
					 1 changed files with 2 additions and 0 deletions
				
			
		|  | @ -804,6 +804,8 @@ void prep_delays(RTLIL::Design *design, bool dff_mode) | |||
| 						log_id(conn.first), log_id(cell->name), log_id(cell->type), log_id(module->name)); | ||||
| 			if (!port_wire->port_input) | ||||
| 				continue; | ||||
| 			if (conn.second.is_fully_const()) | ||||
| 				continue; | ||||
| 
 | ||||
| 			SigSpec O = module->addWire(NEW_ID, GetSize(conn.second)); | ||||
| 			for (int i = 0; i < GetSize(conn.second); i++) { | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue