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qbfsat: Avoid instantiating AttrObjects directly.

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Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
This commit is contained in:
Alberto Gonzalez 2020-06-09 21:31:58 +00:00
parent 08cede4669
commit e1fedf054e
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GPG key ID: 8395A8BA109708B2
1 changed files with 6 additions and 9 deletions
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15
passes/sat/qbfsat.cc
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@ -24,6 +24,7 @@
#include "kernel/rtlil.h" #include "kernel/rtlil.h"
#include "kernel/register.h" #include "kernel/register.h"
#include <algorithm> #include <algorithm>
#include <numeric>
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
@ -98,9 +99,8 @@ void recover_solution(QbfSolutionType &sol) {
log_assert(YS_REGEX_NS::regex_search(loc, hole_loc_regex)); log_assert(YS_REGEX_NS::regex_search(loc, hole_loc_regex));
log_assert(YS_REGEX_NS::regex_search(val, hole_val_regex)); log_assert(YS_REGEX_NS::regex_search(val, hole_val_regex));
#endif #endif
RTLIL::AttrObject tmp; auto locs = split_tokens(loc, "|");
tmp.set_src_attribute(loc); pool<std::string> loc_pool(locs.begin(), locs.end());
pool<std::string> loc_pool = tmp.get_strpool_attribute(ID::src);
sol.hole_to_value[loc_pool] = val; sol.hole_to_value[loc_pool] = val;
} }
else if (YS_REGEX_NS::regex_search(x, sat_regex)) { else if (YS_REGEX_NS::regex_search(x, sat_regex)) {
@ -224,9 +224,7 @@ void write_solution(RTLIL::Module *module, const QbfSolutionType &sol, const std
//SigBit, and "value", which is either '0' or '1', represents the assignment for that bit. //SigBit, and "value", which is either '0' or '1', represents the assignment for that bit.
dict<std::pair<pool<std::string>, int>, RTLIL::SigBit> hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module, sol); dict<std::pair<pool<std::string>, int>, RTLIL::SigBit> hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module, sol);
for (auto &x : sol.hole_to_value) { for (auto &x : sol.hole_to_value) {
RTLIL::AttrObject tmp; std::string src_as_str = std::accumulate(x.first.begin(), x.first.end(), std::string(), [](const std::string &a, const std::string &b){return a + "|" + b;});
tmp.set_strpool_attribute(ID::src, x.first);
std::string src_as_str = tmp.get_string_attribute(ID::src);
for (auto i = 0; i < GetSize(x.second); ++i) for (auto i = 0; i < GetSize(x.second); ++i)
fout << src_as_str.c_str() << " " << i << " " << log_signal(hole_loc_idx_to_sigbit[std::make_pair(x.first, i)]) << " = " << x.second[GetSize(x.second) - 1 - i] << std::endl; fout << src_as_str.c_str() << " " << i << " " << log_signal(hole_loc_idx_to_sigbit[std::make_pair(x.first, i)]) << " = " << x.second[GetSize(x.second) - 1 - i] << std::endl;
} }
@ -281,9 +279,8 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
RTLIL::Wire *hole_wire = module->wire(hole_name); RTLIL::Wire *hole_wire = module->wire(hole_name);
hole_sigbit = RTLIL::SigSpec(hole_wire)[hole_offset]; hole_sigbit = RTLIL::SigSpec(hole_wire)[hole_offset];
} else { } else {
RTLIL::AttrObject tmp; auto locs = split_tokens(hole_loc, "|");
tmp.set_src_attribute(hole_loc); pool<std::string> hole_loc_pool(locs.begin(), locs.end());
pool<std::string> hole_loc_pool = tmp.get_strpool_attribute(ID::src);
auto hole_cell_it = anyconst_loc_to_cell.find(hole_loc_pool); auto hole_cell_it = anyconst_loc_to_cell.find(hole_loc_pool);
if (hole_cell_it == anyconst_loc_to_cell.end()) if (hole_cell_it == anyconst_loc_to_cell.end())
YS_DEBUGTRAP; YS_DEBUGTRAP;