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check: Extend testing

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This commit is contained in:
Martin Povišer 2024-02-12 12:32:15 +01:00
parent b6112b3551
commit e1e77a7fa9
3 changed files with 69 additions and 1 deletions
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33
tests/various/check.ys
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@ -1,5 +1,5 @@
design -reset
read_verilog <<EOF
read -vlog2k <<EOF
module top(input clk, input a, input b, output [9:0] x);
wire [9:0] ripple;
reg [9:0] prev_ripple = 9'b0;
@ -9,4 +9,35 @@ module top(input clk, input a, input b, output [9:0] x);
assign x = ripple[9] + b;
endmodule
EOF
hierarchy -top top
prep
check -assert
design -reset
read -vlog2k <<EOF
module top(clk, y, sideread_addr, sideread_data);
input wire clk;
reg [7:0] mem [255:0];
reg [8:0] i;
initial begin
for (i = 0; i < 256; i = i + 1)
mem[i] = i * 371;
end
output reg [7:0] y = 1;
always @(posedge clk)
y <= mem[y];
input wire [7:0] sideread_addr;
output wire [7:0] sideread_data;
assign sideread_data = mem[sideread_addr];
endmodule
EOF
hierarchy -top top
prep -rdff
select -assert-count 1 t:$mem_v2
check -assert
memory_unpack
select -assert-count 2 t:$memrd_v2
check -assert