async2sync, clk2fflogic: Add support for $check and $print cells

passes/sat/async2sync.cc

@@ -41,31 +41,88 @@ struct Async2syncPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
+		log("    -nolower\n");
+		log("        Do not automatically run 'chformal -lower' to lower $check cells.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		// bool flag_noinit = false;
+		bool flag_nolower = false;
 
 		log_header(design, "Executing ASYNC2SYNC pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-noinit") {
+			if (args[argidx] == "-nolower") {
-			// 	flag_noinit = true;
+				flag_nolower = true;
-			// 	continue;
+				continue;
-			// }
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
+		bool have_check_cells = false;
+
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);
 			FfInitVals initvals(&sigmap, module);
 
+			SigBit initstate;
+
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
+				if (cell->type.in(ID($print), ID($check)))
+				{
+					if (cell->type == ID($check))
+						have_check_cells = true;
+
+					bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
+					if (!trg_enable)
+						continue;
+
+					int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
+
+					if (trg_width > 1)
+						log_error("$check cell %s with TRG_WIDTH > 1 is not support by async2sync, use clk2fflogic.\n", log_id(cell));
+
+					if (trg_width == 0) {
+						if (initstate == State::S0)
+							initstate = module->Initstate(NEW_ID);
+
+						SigBit sig_en = cell->getPort(ID::EN);
+						cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
+					} else {
+						SigBit sig_en = cell->getPort(ID::EN);
+						SigSpec sig_args = cell->getPort(ID::ARGS);
+						bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool();
+						SigBit sig_trg = cell->getPort(ID::TRG);
+						Wire *sig_en_q = module->addWire(NEW_ID);
+						Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args));
+						sig_en_q->attributes.emplace(ID::init, State::S0);
+						module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->get_src_attribute());
+						module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->get_src_attribute());
+						cell->setPort(ID::EN, sig_en_q);
+						cell->setPort(ID::ARGS, sig_args_q);
+						if (cell->type == ID($check)) {
+							SigBit sig_a = cell->getPort(ID::A);
+							Wire *sig_a_q = module->addWire(NEW_ID);
+							sig_a_q->attributes.emplace(ID::init, State::S1);
+							module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->get_src_attribute());
+							cell->setPort(ID::A, sig_a_q);
+						}
+					}
+
+					cell->setPort(ID::TRG, SigSpec());
+
+					cell->setParam(ID::TRG_ENABLE, false);
+					cell->setParam(ID::TRG_WIDTH, 0);
+					cell->setParam(ID::TRG_POLARITY, false);
+					cell->set_bool_attribute(ID(trg_on_gclk));
+					continue;
+				}
+
 				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
 					continue;
 
@@ -273,6 +330,12 @@ struct Async2syncPass : public Pass {
 				ff.emit();
 			}
 		}
+
+		if (have_check_cells && !flag_nolower) {
+			log_push();
+			Pass::call(design, "chformal -lower");
+			log_pop();
+		}
 	}
 } Async2syncPass;
 

passes/sat/clk2fflogic.cc

@@ -48,6 +48,9 @@ struct Clk2fflogicPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
+		log("    -nolower\n");
+		log("        Do not automatically run 'chformal -lower' to lower $check cells.\n");
+		log("\n");
 	}
 	// Active-high sampled and current value of a level-triggered control signal. Initial sampled values is low/non-asserted.
 	SampledSig sample_control(Module *module, SigSpec sig, bool polarity, bool is_fine) {
@@ -117,21 +120,23 @@ struct Clk2fflogicPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		// bool flag_noinit = false;
+		bool flag_nolower = false;
 
 		log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-noinit") {
+			if (args[argidx] == "-nolower") {
-			// 	flag_noinit = true;
+				flag_nolower = true;
-			// 	continue;
+				continue;
-			// }
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
 
+		bool have_check_cells = false;
+
 		for (auto module : design->selected_modules())
 		{
 			SigMap sigmap(module);
@@ -194,10 +199,63 @@ struct Clk2fflogicPass : public Pass {
 				mem.emit();
 			}
 
+			SigBit initstate;
+
 			for (auto cell : vector<Cell*>(module->selected_cells()))
 			{
-				SigSpec qval;
+				if (cell->type.in(ID($print), ID($check)))
-				if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+				{
+					if (cell->type == ID($check))
+						have_check_cells = true;
+
+					bool trg_enable = cell->getParam(ID(TRG_ENABLE)).as_bool();
+					if (!trg_enable)
+						continue;
+
+					int trg_width = cell->getParam(ID(TRG_WIDTH)).as_int();
+
+					if (trg_width == 0) {
+						if (initstate == State::S0)
+							initstate = module->Initstate(NEW_ID);
+
+						SigBit sig_en = cell->getPort(ID::EN);
+						cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
+					} else {
+						SigBit sig_en = cell->getPort(ID::EN);
+						SigSpec sig_args = cell->getPort(ID::ARGS);
+						Const trg_polarity = cell->getParam(ID(TRG_POLARITY));
+						SigSpec sig_trg = cell->getPort(ID::TRG);
+
+						SigSpec sig_trg_sampled;
+
+						for (auto const &bit : sig_trg)
+							sig_trg_sampled.append(sample_control_edge(module, bit, trg_polarity[GetSize(sig_trg_sampled)] == State::S1, false));
+						SigSpec sig_args_sampled = sample_data(module, sig_args, Const(State::S0, GetSize(sig_args)), false, false).sampled;
+						SigBit sig_en_sampled = sample_data(module, sig_en, State::S0, false, false).sampled;
+
+						SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled);
+
+						cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
+						cell->setPort(ID::ARGS, sig_args_sampled);
+						if (cell->type == ID($check)) {
+							SigBit sig_a_sampled = sample_data(module, sig_en, State::S1, false, false).sampled;
+							cell->setPort(ID::A, sig_a_sampled);
+						}
+					}
+
+					cell->setPort(ID::TRG, SigSpec());
+
+					cell->setParam(ID::TRG_ENABLE, false);
+					cell->setParam(ID::TRG_WIDTH, 0);
+					cell->setParam(ID::TRG_POLARITY, false);
+					cell->set_bool_attribute(ID(trg_on_gclk));
+
+					continue;
+				}
+
+				if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+					continue;
+
 				FfData ff(&initvals, cell);
 
 				if (ff.has_gclk) {
@@ -263,10 +321,15 @@ struct Clk2fflogicPass : public Pass {
 				}
 
 				module->connect(ff.sig_q, next_q);
-				}
+
 			}
 		}
 
+		if (have_check_cells && !flag_nolower) {
+			log_push();
+			Pass::call(design, "chformal -lower");
+			log_pop();
+		}
 	}
 } Clk2fflogicPass;
 

tests/various/chformal_coverenable.ys

@@ -13,6 +13,8 @@ EOT
 
 prep -top top
 
+design -save prep
+
 async2sync
 
 select -assert-count 1 t:$cover