mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00
Code Activity

Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards

Browse source 
Just like Verilog...
This commit is contained in:
Eddie Hung 2020-01-27 14:02:13 -08:00
parent cfb0366a18
commit e18aeda7ed
2 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/pmgen/ice40_wrapcarry.cc
View file

@ -127,7 +127,7 @@ struct Ice40WrapCarryPass : public Pass {
lut->setParam(ID(WIDTH), 4);
lut->setParam(ID(LUT), cell->getParam(ID(LUT)));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3));
lut->setPort(ID(A), {cell->getPort(ID(I0)), cell->getPort(ID(A)), cell->getPort(ID(B)), I3 });
lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) });
lut->setPort(ID(Y), cell->getPort(ID(O)));
Const src;

2
techlibs/ice40/ice40_opt.cc
View file

@ -140,7 +140,7 @@ static void run_ice40_opts(Module *module)
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 });
cell->setPort("\\A", { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
cell->setPort("\\Y", cell->getPort("\\O"));
cell->unsetPort("\\B");
cell->unsetPort("\\CI");