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verilog: add support for SystemVerilog string literals.

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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
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Gary Wong 2025-07-03 20:51:12 -06:00 • committed by Emil J. Tywoniak
parent a519390fc4
commit e17ed5df88
4 changed files with 385 additions and 47 deletions
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docs/source/yosys_internals/verilog.rst
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@ -381,3 +381,6 @@ from SystemVerilog:
will process conditionals using these keywords by annotating their
representation with the appropriate ``full_case`` and/or ``parallel_case``
attributes, which are described above.)
- SystemVerilog string literals are supported (triple-quoted strings and
escape sequences such as line continuations and hex escapes).