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	Merge pull request #2658 from zachjs/parameters-across-files
sv: allow globals in one file to depend on globals in another
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						e178d0367a
					
				
					 3 changed files with 21 additions and 1 deletions
				
			
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					@ -1288,7 +1288,6 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
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			// must be global definition
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								// must be global definition
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			if ((*it)->type == AST_PARAMETER)
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								if ((*it)->type == AST_PARAMETER)
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				(*it)->type = AST_LOCALPARAM; // cannot be overridden
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									(*it)->type = AST_LOCALPARAM; // cannot be overridden
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			(*it)->simplify(false, false, false, 1, -1, false, false); //process enum/other declarations
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			design->verilog_globals.push_back((*it)->clone());
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								design->verilog_globals.push_back((*it)->clone());
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			current_scope.clear();
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								current_scope.clear();
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		}
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							}
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					@ -192,6 +192,7 @@ void AstNode::annotateTypedEnums(AstNode *template_node)
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		log_assert(current_scope.count(enum_type) == 1);
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							log_assert(current_scope.count(enum_type) == 1);
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		AstNode *enum_node = current_scope.at(enum_type);
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							AstNode *enum_node = current_scope.at(enum_type);
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		log_assert(enum_node->type == AST_ENUM);
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							log_assert(enum_node->type == AST_ENUM);
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							while (enum_node->simplify(true, false, false, 1, -1, false, true)) { }
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		//get width from 1st enum item:
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							//get width from 1st enum item:
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		log_assert(enum_node->children.size() >= 1);
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							log_assert(enum_node->children.size() >= 1);
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		AstNode *enum_item0 = enum_node->children[0];
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							AstNode *enum_item0 = enum_node->children[0];
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										20
									
								
								tests/verilog/parameters_across_files.ys
									
										
									
									
									
										Normal file
									
								
							
							
						
						
									
										20
									
								
								tests/verilog/parameters_across_files.ys
									
										
									
									
									
										Normal file
									
								
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					@ -0,0 +1,20 @@
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					read_verilog -sv <<EOF
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					parameter Q = 1;
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					EOF
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					read_verilog -sv <<EOF
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					parameter P = Q;
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					module top(
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					    output integer out
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					);
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					    assign out = P;
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					    always @*
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					        assert (out == 1);
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					endmodule
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					EOF
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					hierarchy
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					proc
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					flatten
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					opt -full
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					select -module top
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					sat -verify -seq 1 -tempinduct -prove-asserts -show-all
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