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add $priority cell

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This commit is contained in:
Emil J. Tywoniak 2026-01-09 18:43:15 +01:00
parent 967b47d984
commit e166dd4475
9 changed files with 136 additions and 2 deletions
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16
techlibs/common/simlib.v
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@ -3250,3 +3250,19 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y;
endmodule
// --------------------------------------------------------
//-
//- $priority (A, Y)
//* group unary
//-
//- Priority operator. An output bit is set if the input bit at the same index is set and no lower index input bit is set.
//-
module \$priority (A, Y);
parameter WIDTH = 8;
input [WIDTH-1:0] A;
output [WIDTH-1:0] Y;
assign Y = A & (~A + 1);
endmodule

26
techlibs/common/techmap.v
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@ -679,3 +679,29 @@ parameter WIDTH = 0;
inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
endmodule
(* techmap_celltype = "$priority" *)
module \$priority (A, Y);
parameter WIDTH = 3;
(* force_downto *)
input [WIDTH-1:0] A;
(* force_downto *)
output [WIDTH-1:0] Y;
(* force_downto *)
wire [WIDTH-1:0] tmp;
genvar i;
generate
if (WIDTH > 0) begin
assign tmp[0] = A[0];
assign Y[0] = A[0];
end
for (i = 1; i < WIDTH; i = i + 1) begin
assign Y[i] = A[i] & ~tmp[i-1];
assign tmp[i] = tmp[i-1] | A[i];
end
endgenerate
endmodule