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https://github.com/YosysHQ/yosys
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Add log_debug() framework
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
c0f9a74b12
commit
e158ea2097
11 changed files with 183 additions and 53 deletions
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@ -67,7 +67,7 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
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if (sig.size() == 0)
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continue;
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log("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
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log_debug("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
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module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
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did_something = true;
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}
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@ -78,7 +78,7 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
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RTLIL::SigSpec Y = cell->getPort(out_port);
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out_val.extend_u0(Y.size(), false);
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log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
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log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
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cell->type.c_str(), cell->name.c_str(), info.c_str(),
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module->name.c_str(), log_signal(Y), log_signal(out_val));
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// log_cell(cell);
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@ -134,7 +134,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
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if (GetSize(grouped_bits[i]) == GetSize(bits_y))
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return false;
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log("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
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log_debug("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
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log_id(cell->type), log_id(cell), log_id(module));
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for (int i = 0; i < GRP_N; i++)
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@ -156,7 +156,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
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}
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if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
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log(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
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log_debug(" Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
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module->connect(new_y, new_b);
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module->connect(new_conn);
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continue;
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@ -180,10 +180,10 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
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module->connect(new_conn);
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log(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
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log_debug(" New cell `%s': A=%s", log_id(c), log_signal(new_a));
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if (b_name == "\\B")
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log(", B=%s", log_signal(new_b));
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log("\n");
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log_debug(", B=%s", log_signal(new_b));
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log_debug("\n");
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}
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cover_list("opt.opt_expr.fine.group", "$not", "$pos", "$and", "$or", "$xor", "$xnor", cell->type.str());
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@ -197,7 +197,7 @@ void handle_polarity_inv(Cell *cell, IdString port, IdString param, const SigMap
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{
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SigSpec sig = assign_map(cell->getPort(port));
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if (invert_map.count(sig)) {
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log("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
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log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
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log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
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log_signal(sig), log_signal(invert_map.at(sig)));
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cell->setPort(port, (invert_map.at(sig)));
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@ -226,7 +226,7 @@ void handle_clkpol_celltype_swap(Cell *cell, string type1, string type2, IdStrin
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if (cell->type.in(type1, type2)) {
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SigSpec sig = assign_map(cell->getPort(port));
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if (invert_map.count(sig)) {
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log("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
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log_debug("Inverting %s of %s cell `%s' in module `%s': %s -> %s\n",
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log_id(port), log_id(cell->type), log_id(cell), log_id(cell->module),
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log_signal(sig), log_signal(invert_map.at(sig)));
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cell->setPort(port, (invert_map.at(sig)));
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@ -455,9 +455,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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{
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if (cell->type == "$reduce_xnor") {
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cover("opt.opt_expr.reduce_xnor_not");
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log("Replacing %s cell `%s' in module `%s' with $not cell.\n",
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log_debug("Replacing %s cell `%s' in module `%s' with $not cell.\n",
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log_id(cell->type), log_id(cell->name), log_id(module));
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cell->type = "$not";
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did_something = true;
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} else {
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cover("opt.opt_expr.unary_buffer");
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replace_cell(assign_map, module, cell, "unary_buffer", "\\Y", cell->getPort("\\A"));
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@ -488,7 +489,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (GetSize(new_sig_a) < GetSize(sig_a)) {
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cover_list("opt.opt_expr.fine.neutral_A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_and", "$reduce_bool", cell->type.str());
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log("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
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log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
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cell->setPort("\\A", new_sig_a);
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cell->parameters.at("\\A_WIDTH") = GetSize(new_sig_a);
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@ -511,7 +512,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (GetSize(new_sig_b) < GetSize(sig_b)) {
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cover_list("opt.opt_expr.fine.neutral_B", "$logic_and", "$logic_or", cell->type.str());
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log("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
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log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
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cell->setPort("\\B", new_sig_b);
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cell->parameters.at("\\B_WIDTH") = GetSize(new_sig_b);
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@ -537,7 +538,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
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cover("opt.opt_expr.fine.$reduce_and");
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log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
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cell->setPort("\\A", sig_a = new_a);
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cell->parameters.at("\\A_WIDTH") = 1;
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@ -563,7 +564,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
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cover_list("opt.opt_expr.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str());
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log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
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cell->setPort("\\A", sig_a = new_a);
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cell->parameters.at("\\A_WIDTH") = 1;
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@ -589,7 +590,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) {
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cover_list("opt.opt_expr.fine.B", "$logic_and", "$logic_or", cell->type.str());
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log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
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cell->setPort("\\B", sig_b = new_b);
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cell->parameters.at("\\B_WIDTH") = 1;
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@ -640,7 +641,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
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cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
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log("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
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log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
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RTLIL::SigSpec tmp = cell->getPort("\\A");
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cell->setPort("\\A", cell->getPort("\\B"));
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cell->setPort("\\B", tmp);
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@ -750,7 +751,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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ACTION_DO("\\Y", cell->getPort("\\A"));
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if (input == State::S0 && !a.is_fully_undef()) {
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cover("opt.opt_expr.action_" S__LINE__);
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log("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
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log_debug("Replacing data input of %s cell `%s' in module `%s' with constant undef.\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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cell->setPort("\\A", SigSpec(State::Sx, GetSize(a)));
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did_something = true;
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@ -822,7 +823,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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ACTION_DO("\\Y", cell->getPort("\\A"));
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} else {
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cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
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log("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
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log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
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cell->type = "$not";
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cell->parameters.erase("\\B_WIDTH");
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cell->parameters.erase("\\B_SIGNED");
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@ -837,7 +838,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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(assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero()))
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{
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cover_list("opt.opt_expr.eqneq.cmpzero", "$eq", "$ne", cell->type.str());
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log("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
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log_debug("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell),
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log_id(module), "$eq" ? "$logic_not" : "$reduce_bool");
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cell->type = cell->type == "$eq" ? "$logic_not" : "$reduce_bool";
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if (assign_map(cell->getPort("\\A")).is_fully_zero()) {
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@ -876,7 +877,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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cover_list("opt.opt_expr.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str());
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log("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
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log_debug("Replacing %s cell `%s' (B=%s, SHR=%d) in module `%s' with fixed wiring: %s\n",
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log_id(cell->type), log_id(cell), log_signal(assign_map(cell->getPort("\\B"))), shift_bits, log_id(module), log_signal(sig_y));
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module->connect(cell->getPort("\\Y"), sig_y);
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@ -939,7 +940,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (identity_wrt_b)
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cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
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log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
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log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
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if (!identity_wrt_a) {
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@ -969,7 +970,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
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cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
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cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
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log("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
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log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
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cell->setPort("\\A", cell->getPort("\\S"));
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cell->unsetPort("\\B");
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cell->unsetPort("\\S");
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@ -988,7 +989,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
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cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
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log("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
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log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
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cell->setPort("\\A", cell->getPort("\\S"));
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cell->unsetPort("\\S");
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if (cell->type == "$mux") {
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@ -1008,7 +1009,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
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cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
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log("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
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log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
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cell->setPort("\\B", cell->getPort("\\S"));
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cell->unsetPort("\\S");
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if (cell->type == "$mux") {
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@ -1061,7 +1062,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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if (cell->getPort("\\S").size() != new_s.size()) {
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cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
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log("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
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log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
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GetSize(cell->getPort("\\S")) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
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cell->setPort("\\A", new_a);
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cell->setPort("\\B", new_b);
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@ -1179,7 +1180,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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{
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cover("opt.opt_expr.mul_shift.zero");
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log("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
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log_debug("Replacing multiply-by-zero cell `%s' in module `%s' with zero-driver.\n",
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cell->name.c_str(), module->name.c_str());
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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@ -1197,7 +1198,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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else
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cover("opt.opt_expr.mul_shift.unswapped");
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log("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
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log_debug("Replacing multiply-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
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a_val, cell->name.c_str(), module->name.c_str(), i);
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if (!swapped_ab) {
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@ -1237,7 +1238,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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{
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cover("opt.opt_expr.divmod_zero");
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log("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n",
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log_debug("Replacing divide-by-zero cell `%s' in module `%s' with undef-driver.\n",
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cell->name.c_str(), module->name.c_str());
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module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(State::Sx, sig_y.size())));
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@ -1254,7 +1255,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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{
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cover("opt.opt_expr.div_shift");
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log("Replacing divide-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
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log_debug("Replacing divide-by-%d cell `%s' in module `%s' with shift-by-%d.\n",
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b_val, cell->name.c_str(), module->name.c_str(), i);
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std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
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@ -1272,7 +1273,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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{
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cover("opt.opt_expr.mod_mask");
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log("Replacing modulo-by-%d cell `%s' in module `%s' with bitmask.\n",
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log_debug("Replacing modulo-by-%d cell `%s' in module `%s' with bitmask.\n",
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b_val, cell->name.c_str(), module->name.c_str());
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std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(State::S1, i);
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@ -1342,7 +1343,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
SigSpec y_sig = cell->getPort("\\Y");
|
||||
Const y_value(cell->type.in("$eq", "$eqx") ? 0 : 1, GetSize(y_sig));
|
||||
|
||||
log("Replacing cell `%s' in module `%s' with constant driver %s.\n",
|
||||
log_debug("Replacing cell `%s' in module `%s' with constant driver %s.\n",
|
||||
log_id(cell), log_id(module), log_signal(y_value));
|
||||
|
||||
module->connect(y_sig, y_value);
|
||||
|
|
@ -1354,7 +1355,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
|
||||
if (redundant_bits)
|
||||
{
|
||||
log("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
|
||||
log_debug("Removed %d redundant input bits from %s cell `%s' in module `%s'.\n",
|
||||
redundant_bits, log_id(cell->type), log_id(cell), log_id(module));
|
||||
|
||||
cell->setPort("\\A", sig_a);
|
||||
|
|
@ -1493,7 +1494,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
|
|||
|
||||
if (replace || remove)
|
||||
{
|
||||
log("Replacing %s cell `%s' (implementing %s) with %s.\n",
|
||||
log_debug("Replacing %s cell `%s' (implementing %s) with %s.\n",
|
||||
log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
|
||||
if (replace)
|
||||
module->connect(cell->getPort("\\Y"), replace_sig);
|
||||
|
|
@ -1599,8 +1600,14 @@ struct OptExprPass : public Pass {
|
|||
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
if (undriven)
|
||||
log("Optimizing module %s.\n", log_id(module));
|
||||
|
||||
if (undriven) {
|
||||
did_something = false;
|
||||
replace_undriven(design, module);
|
||||
if (did_something)
|
||||
design->scratchpad_set_bool("opt.did_something", true);
|
||||
}
|
||||
|
||||
do {
|
||||
do {
|
||||
|
|
@ -1610,7 +1617,11 @@ struct OptExprPass : public Pass {
|
|||
design->scratchpad_set_bool("opt.did_something", true);
|
||||
} while (did_something);
|
||||
replace_const_cells(design, module, true, mux_undef, mux_bool, do_fine, keepdc, clkinv);
|
||||
if (did_something)
|
||||
design->scratchpad_set_bool("opt.did_something", true);
|
||||
} while (did_something);
|
||||
|
||||
log_suppressed();
|
||||
}
|
||||
|
||||
log_pop();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue