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Added $equiv cell type

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Clifford Wolf 2015-01-19 11:55:05 +01:00
parent 3a58b8d5b5
commit e13a45ae61
4 changed files with 33 additions and 2 deletions
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1
kernel/celltypes.h
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@ -114,6 +114,7 @@ struct CellTypes
setup_type("$fa", {A, B, C}, {X, Y}, true);
setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$equiv", {A, B}, {Y}, true);
}
void setup_internals_mem()

8
kernel/rtlil.cc
View file

@ -905,6 +905,14 @@ namespace {
return;
}
if (cell->type == "$equiv") {
port("\\A", 1);
port("\\B", 1);
port("\\Y", 1);
check_expected();
return;
}
if (cell->type == "$_BUF_") { check_gate("AY"); return; }
if (cell->type == "$_NOT_") { check_gate("AY"); return; }
if (cell->type == "$_AND_") { check_gate("ABY"); return; }

2
manual/CHAPTER_CellLib.tex
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@ -417,7 +417,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
using the {\tt abc} pass.
\begin{fixme}
Add information about {\tt \$assert} cells.
Add information about {\tt \$assert} and {\tt \$equiv} cells.
\end{fixme}
\begin{fixme}

24
techlibs/common/simlib.v
View file

@ -1160,12 +1160,34 @@ module \$assert (A, EN);
input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'b1 && EN === 1'b1) begin
$display("Assertation failed!");
$finish;
$stop;
end
end
`endif
endmodule
// --------------------------------------------------------
module \$equiv (A, B, Y);
input A, B;
output Y;
assign Y = (A !== 1'bx && A !== B) ? 1'bx : A;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A !== 1'bx && A !== B) begin
$display("Equivalence failed!");
$stop;
end
end
`endif
endmodule