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Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_

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This commit is contained in:
Clifford Wolf 2013-10-18 12:13:34 +02:00
parent 5998c101a4
commit e0f693cbb0
3 changed files with 181 additions and 0 deletions
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1
backends/verilog/verilog_backend.cc
View file

@ -573,6 +573,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
// FIXME: $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
// FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm // FIXME: $sr, $dffsr, $dlatch, $memrd, $memwr, $mem, $fsm
return false; return false;

14
kernel/celltypes.h
View file

@ -119,6 +119,10 @@ struct CellTypes
void setup_stdcells_mem() void setup_stdcells_mem()
{ {
cell_types.insert("$_SR_NN_");
cell_types.insert("$_SR_NP_");
cell_types.insert("$_SR_PN_");
cell_types.insert("$_SR_PP_");
cell_types.insert("$_DFF_N_"); cell_types.insert("$_DFF_N_");
cell_types.insert("$_DFF_P_"); cell_types.insert("$_DFF_P_");
cell_types.insert("$_DFF_NN0_"); cell_types.insert("$_DFF_NN0_");
@ -129,6 +133,16 @@ struct CellTypes
cell_types.insert("$_DFF_PN1_"); cell_types.insert("$_DFF_PN1_");
cell_types.insert("$_DFF_PP0_"); cell_types.insert("$_DFF_PP0_");
cell_types.insert("$_DFF_PP1_"); cell_types.insert("$_DFF_PP1_");
cell_types.insert("$_DFFSR_NNN_");
cell_types.insert("$_DFFSR_NNP_");
cell_types.insert("$_DFFSR_NPN_");
cell_types.insert("$_DFFSR_NPP_");
cell_types.insert("$_DFFSR_PNN_");
cell_types.insert("$_DFFSR_PNP_");
cell_types.insert("$_DFFSR_PPN_");
cell_types.insert("$_DFFSR_PPP_");
cell_types.insert("$_DLATCH_N_");
cell_types.insert("$_DLATCH_P_");
} }
void clear() void clear()

166
techlibs/common/stdcells_sim.v
View file

@ -60,6 +60,50 @@ always @* begin
end end
endmodule endmodule
module \$_SR_NN_ (S, R, Q);
input S, R;
output reg Q;
always @(negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
end
endmodule
module \$_SR_NP_ (S, R, Q);
input S, R;
output reg Q;
always @(negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
end
endmodule
module \$_SR_PN_ (S, R, Q);
input S, R;
output reg Q;
always @(posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
end
endmodule
module \$_SR_PP_ (S, R, Q);
input S, R;
output reg Q;
always @(posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
end
endmodule
module \$_DFF_N_ (D, Q, C); module \$_DFF_N_ (D, Q, C);
input D, C; input D, C;
output reg Q; output reg Q;
@ -164,3 +208,125 @@ always @(posedge C or posedge R) begin
end end
endmodule endmodule
module \$_DFFSR_NNN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_NNP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_NPN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_NPP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(negedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_PNN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, negedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_PNP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, negedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 0)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_PPN_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, posedge S, negedge R) begin
if (R == 0)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DFFSR_PPP_ (C, S, R, D, Q);
input C, S, R, D;
output reg Q;
always @(posedge C, posedge S, posedge R) begin
if (R == 1)
Q <= 0;
else if (S == 1)
Q <= 1;
else
Q <= D;
end
endmodule
module \$_DLATCH_N_ (E, D, Q);
input E, D;
output reg Q;
always @* begin
if (E == 0)
Q <= D;
end
endmodule
module \$_DLATCH_P_ (E, D, Q);
input E, D;
output reg Q;
always @* begin
if (E == 1)
Q <= D;
end
endmodule