diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 81c72205e..82b7e6632 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1532,7 +1532,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma FOREACH_PARAMETER_OF_NETLIST(nl, mi, param_name, param_value) { module->avail_parameters(RTLIL::escape_id(param_name)); const TypeRange *tr = nl->GetTypeRange(param_name) ; - module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(tr->GetTypeName(), param_value, nl); + const char* type_name = (tr) ? tr->GetTypeName() : nullptr; + module->parameter_default_values[RTLIL::escape_id(param_name)] = verific_const(type_name, param_value, nl); } SetIter si; @@ -2232,7 +2233,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (is_blackbox(inst->View())) { FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) { const TypeRange *tr = inst->View()->GetTypeRange(param_name) ; - cell->setParam(RTLIL::escape_id(param_name), verific_const(tr->GetTypeName(), param_value, inst->View())); + const char* type_name = (tr) ? tr->GetTypeName() : nullptr; + cell->setParam(RTLIL::escape_id(param_name), verific_const(type_name, param_value, inst->View())); } } diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 940884353..468181991 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -106,28 +106,28 @@ static std::pair, std::optional> if (pin->id != "pin" || pin->args.size() != 1) continue; - if (auto clk = pin->find("clock_gate_clock_pin")) { + if (pin->find("clock_gate_clock_pin")) { if (!icg_interface.clk_in_pin.empty()) { log_warning("Malformed liberty file - multiple clock_gate_clock_pin in cell %s\n", cell_name.c_str()); continue; } else icg_interface.clk_in_pin = RTLIL::escape_id(pin->args[0]); - } else if (auto gclk = pin->find("clock_gate_out_pin")) { + } else if (pin->find("clock_gate_out_pin")) { if (!icg_interface.clk_out_pin.empty()) { log_warning("Malformed liberty file - multiple clock_gate_out_pin in cell %s\n", cell_name.c_str()); continue; } else icg_interface.clk_out_pin = RTLIL::escape_id(pin->args[0]); - } else if (auto en = pin->find("clock_gate_enable_pin")) { + } else if (pin->find("clock_gate_enable_pin")) { if (!icg_interface.ce_pin.empty()) { log_warning("Malformed liberty file - multiple clock_gate_enable_pin in cell %s\n", cell_name.c_str()); continue; } else icg_interface.ce_pin = RTLIL::escape_id(pin->args[0]); - } else if (auto se = pin->find("clock_gate_test_pin")) { + } else if (pin->find("clock_gate_test_pin")) { icg_interface.tie_lo_pins.push_back(RTLIL::escape_id(pin->args[0])); } else { const LibertyAst *dir = pin->find("direction"); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 8af4f6a04..b6c340c00 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -116,7 +116,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std if (tree.kind == LibertyExpression::Kind::EMPTY) { if (!warned_cells.count(cell_name)) { - log_warning("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr.c_str(), cell_name.c_str()); + log_debug("Invalid expression '%s' in next_state attribute of cell '%s' - skipping.\n", expr.c_str(), cell_name.c_str()); warned_cells.insert(cell_name); } return false; @@ -135,7 +135,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std // position that gives better diagnostics here. if (!pin_names.count(ff_output)) { if (!warned_cells.count(cell_name)) { - log_warning("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr.c_str(), cell_name.c_str(), ff_output.c_str()); + log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not contain ff output '%s' - skipping.\n", expr.c_str(), cell_name.c_str(), ff_output.c_str()); warned_cells.insert(cell_name); } return false; @@ -184,7 +184,7 @@ static bool parse_next_state(const LibertyAst *cell, const LibertyAst *attr, std } if (!warned_cells.count(cell_name)) { - log_warning("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr.c_str(), cell_name.c_str()); + log_debug("Inference failed on expression '%s' in next_state attribute of cell '%s' because it does not evaluate to an enable flop - skipping.\n", expr.c_str(), cell_name.c_str()); warned_cells.insert(cell_name); } return false; @@ -220,10 +220,10 @@ static bool parse_pin(const LibertyAst *cell, const LibertyAst *attr, std::strin For now, we'll simply produce a warning to let the user know something is up. */ if (pin_name.find_first_of("^*|&") == std::string::npos) { - log_warning("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + log_debug("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); } else { - log_warning("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); + log_debug("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str()); } return false; diff --git a/techlibs/common/choices/han-carlson.v b/techlibs/common/choices/han-carlson.v index 2ddcf75e9..0ce8ee207 100644 --- a/techlibs/common/choices/han-carlson.v +++ b/techlibs/common/choices/han-carlson.v @@ -13,6 +13,8 @@ module _80_lcu_han_carlson (P, G, CI, CO); (* force_downto *) reg [WIDTH-1:0] p, g; + wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast"; + always @* begin i = 0; p = P;