From e0ce4b42f6b3a4a5a1ac87892cfa24035aa78724 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Mon, 5 Jan 2026 23:32:23 +0530 Subject: [PATCH] fix for VHDL default library path handling --- frontends/verific/verific.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 886c28093..59ee7ea03 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3692,15 +3692,15 @@ struct VerificPass : public Pass { break; } -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { - for (argidx++; argidx < GetSize(args); argidx++) { #ifdef VERIFIC_VHDL_SUPPORT + if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { + for (argidx++; argidx < GetSize(args); argidx++) vhdl_file::SetDefaultLibraryPath(args[argidx].c_str()); -#endif - } goto check_error; } +#endif + +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED;