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presentation progress
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@ -423,7 +423,70 @@ more advanced ABC features. It is also possible to write the design with
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\subsection{Other special-purpose mapping commands}
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\begin{frame}{\subsecname}
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TBD
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\begin{block}{\tt dfflibmap}
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This command maps the internal register cell types to the register types
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described in a liberty file.
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\end{block}
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\bigskip
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\begin{block}{\tt hilomap}
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Some architectures require special driver cells for driving a constant hi or lo
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value. This command replaces simple constants with instances of such driver cells.
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\end{block}
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\bigskip
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\begin{block}{\tt iopadmap}
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Top-level input/outputs must usually be implemented using special I/O-pad cells.
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This command inserts this cells to the design.
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\end{block}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\subsection{Example Synthesis Script}
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\begin{frame}[fragile]{\subsecname}
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\begin{columns}
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\column[t]{4cm}
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\begin{lstlisting}[basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont]
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# read and elaborate design
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read_verilog cpu_top.v cpu_ctrl.v cpu_regs.v
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read_verilog -D WITH_MULT cpu_alu.v
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hierarchy -check -top cpu_top
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# high-level synthesis
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proc; opt; memory -nomap;; fsm; opt
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# substitute block rams
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techmap -map map_rams.v
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# map remaining memories
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memory_map
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# low-level synthesis
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techmap; opt; flatten;; abc -lut6
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techmap -map map_xl_cells.v
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# add clock buffers
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select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d
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iopadmap -inpad BUFGP O:I @xl_clocks
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# add io buffers
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select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d
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iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks
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# write synthesis results
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write_edif synth.edif
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\end{lstlisting}
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\column[t]{6cm}
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\begin{block}{Teaser / Outlook}
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\small\parbox{6cm}{
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This script contains some constructs that have not been explained
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so far, such as the weird {\tt select} expressions at the end of
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the script. They are only one of the topics covered in Section 3
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``Advanced Synthesis'' of this presentation.}
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\end{block}
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\end{columns}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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