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Fix DSP48E1 timing by breaking P path if MREG or PREG

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This commit is contained in:
Eddie Hung 2019-09-19 18:59:28 -07:00
parent 362a803779
commit e09f80479e
4 changed files with 363 additions and 349 deletions
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6
techlibs/xilinx/abc_unmap.v
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@ -32,12 +32,14 @@ module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q);
endmodule
(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)
module \$__ABC_DSP48E1_MUX (
input Aq, Bq, Cq, Dq, ADq, Mq,
input Aq, Bq, Cq, Dq, ADq,
input [47:0] I,
input Mq,
input [47:0] P,
input Pq,
output [47:0] O
);
assign O = P;
assign O = I;
endmodule
(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *)