mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-11-04 05:19:11 +00:00 
			
		
		
		
	If init is 1'bx, do not add to dict as per @cliffordwolf
This commit is contained in:
		
							parent
							
								
									fc349de033
								
							
						
					
					
						commit
						e08df0c739
					
				
					 1 changed files with 2 additions and 1 deletions
				
			
		| 
						 | 
				
			
			@ -102,7 +102,8 @@ struct DffinitPass : public Pass {
 | 
			
		|||
				if (wire->attributes.count("\\init")) {
 | 
			
		||||
					Const value = wire->attributes.at("\\init");
 | 
			
		||||
					for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
 | 
			
		||||
						init_bits[sigmap(SigBit(wire, i))] = value[i];
 | 
			
		||||
						if (value[i] != State::Sx)
 | 
			
		||||
							init_bits[sigmap(SigBit(wire, i))] = value[i];
 | 
			
		||||
				}
 | 
			
		||||
				if (wire->port_output)
 | 
			
		||||
					for (auto bit : sigmap(wire))
 | 
			
		||||
| 
						 | 
				
			
			
 | 
			
		|||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue