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Check abc_box_id attr

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This commit is contained in:
Eddie Hung 2019-04-15 22:25:37 -07:00
parent 8fbbd9b129
commit e084240a81
1 changed files with 16 additions and 1 deletions
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17
backends/aiger/xaiger.cc
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@ -212,6 +212,8 @@ struct XAigerWriter
continue; continue;
} }
bool abc_box = module->design->module(cell->type)->attributes.count("\\abc_box_id");
for (const auto &c : cell->connections()) { for (const auto &c : cell->connections()) {
/*if (c.second.is_fully_const()) continue;*/ /*if (c.second.is_fully_const()) continue;*/
for (auto b : c.second.bits()) { for (auto b : c.second.bits()) {
@ -224,20 +226,33 @@ struct XAigerWriter
if (I != b) if (I != b)
alias_map[b] = I; alias_map[b] = I;
/*if (!output_bits.count(b))*/ /*if (!output_bits.count(b))*/
if (abc_box)
co_bits.emplace_back(b, 0); co_bits.emplace_back(b, 0);
else {
output_bits.insert(b);
if (!b.wire->port_input)
unused_bits.erase(b);
}
} }
} }
if (is_output) { if (is_output) {
SigBit O = sigmap(b); SigBit O = sigmap(b);
/*if (!input_bits.count(O))*/ /*if (!input_bits.count(O))*/
if (abc_box)
ci_bits.emplace_back(O, 0); ci_bits.emplace_back(O, 0);
else {
input_bits.insert(O);
if (!O.wire->port_output)
undriven_bits.erase(O);
}
} }
} }
if (!type_map.count(cell->type)) if (!type_map.count(cell->type))
type_map[cell->type] = type_map.size()+1; type_map[cell->type] = type_map.size()+1;
} }
box_list.emplace_back(cell); if (abc_box)
box_list.emplace_back(cell);
//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
} }