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Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data
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e3664066d5
commit
e07698818d
4 changed files with 35 additions and 38 deletions
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@ -864,7 +864,7 @@ public:
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struct RTLIL::SigChunk
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{
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RTLIL::Wire *wire;
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RTLIL::Const data; // only used if wire == NULL, LSB at index 0
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std::vector<RTLIL::State> data; // only used if wire == NULL, LSB at index 0
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int width, offset;
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SigChunk();
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@ -895,8 +895,8 @@ struct RTLIL::SigBit
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SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
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SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
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SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
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SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; }
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SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }
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SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
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SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
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SigBit(const RTLIL::SigSpec &sig);
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bool operator <(const RTLIL::SigBit &other) const {
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