mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Added missing newline to some error messages
This commit is contained in:
		
							parent
							
								
									6a38e767ba
								
							
						
					
					
						commit
						e04d88cf22
					
				
					 1 changed files with 2 additions and 2 deletions
				
			
		|  | @ -73,10 +73,10 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, | |||
| 	log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name)); | ||||
| 
 | ||||
| 	if (tpl->memories.size() != 0) | ||||
| 		log_error("Technology map yielded memories -> this is not supported."); | ||||
| 		log_error("Technology map yielded memories -> this is not supported.\n"); | ||||
| 
 | ||||
| 	if (tpl->processes.size() != 0) | ||||
| 		log_error("Technology map yielded processes -> this is not supported."); | ||||
| 		log_error("Technology map yielded processes -> this is not supported.\n"); | ||||
| 
 | ||||
| 	for (auto &it : tpl->wires) { | ||||
| 		RTLIL::Wire *w = new RTLIL::Wire(*it.second); | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue