mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 09:05:32 +00:00
Code Activity

Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%.

Browse source
This commit is contained in:
Rasmus Munk Larsen 2023-09-20 15:49:05 -07:00
parent 8fb807cd24
commit e0042bdff7
5 changed files with 126 additions and 79 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/glift.cc
View file

@ -582,7 +582,7 @@ struct GliftPass : public Pass {
for (auto cell : module->selected_cells()) {
RTLIL::Module *tpl = design->module(cell->type);
if (tpl != nullptr) {
if (topo_modules.database.count(tpl) == 0)
if (!topo_modules.has_edges(tpl))
worklist.push_back(tpl);
topo_modules.edge(tpl, module);
non_top_modules.insert(cell->type);

15
passes/opt/opt_expr.cc
View file

@ -424,13 +424,18 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
for (auto &bit : sig)
outbit_to_cell[bit].insert(cell);
}
cells.node(cell);
}
for (auto &it_right : cell_to_inbit)
for (auto &it_sigbit : it_right.second)
for (auto &it_left : outbit_to_cell[it_sigbit])
cells.edge(it_left, it_right.first);
// Build the graph for the topological sort.
for (auto &it_right : cell_to_inbit) {
const int r_index = cells.node(it_right.first);
for (auto &it_sigbit : it_right.second) {
for (auto &it_left : outbit_to_cell[it_sigbit]) {
const int l_index = cells.node(it_left);
cells.edge(l_index, r_index);
}
}
}
cells.sort();

2
passes/opt/share.cc
View file

@ -1032,7 +1032,7 @@ struct ShareWorker
}
bool found_scc = !toposort.sort();
topo_cell_drivers = std::move(toposort.database);
topo_cell_drivers = toposort.get_database();
if (found_scc && toposort.analyze_loops)
for (auto &loop : toposort.loops) {

2
passes/techmap/flatten.cc
View file

@ -312,7 +312,7 @@ struct FlattenPass : public Pass {
for (auto cell : module->selected_cells()) {
RTLIL::Module *tpl = design->module(cell->type);
if (tpl != nullptr) {
if (topo_modules.database.count(tpl) == 0)
if (!topo_modules.has_edges(tpl))
worklist.insert(tpl);
topo_modules.edge(tpl, module);
}