Docs: Comments from @jix

- Unswap shift/shiftx
- Add brief overview to cell lib
- Clarify $div cell B input
- Clarify unary operators
- What is $modfloor

docs/source/cell/properties.rst

@@ -15,6 +15,7 @@ Cell properties
 .. cell:defprop:: x-output
 
    These cells can produce 'x' output even if all inputs are defined.  For
-   example, a `$div` cell with ``B=0`` has undefined output.
+   example, a `$div` cell with divisor (``B``) equal to zero has undefined
+   output.
 
 Refer to the :ref:`propindex` for the list of cells with a given property.

docs/source/cell/word_binary.rst

@@ -66,8 +66,8 @@ Division and modulo cells are available in two rounding modes. The original
 `$div` and `$mod` cells are based on truncating division, and correspond to the
 semantics of the verilog ``/`` and ``%`` operators. The `$divfloor` and
 `$modfloor` cells represent flooring division and flooring modulo, the latter of
-which is also known as "remainder" in several languages. See the following table
+which corresponds to the ``%`` operator in Python. See the following table for a
-for a side-by-side comparison between the different semantics.
+side-by-side comparison between the different semantics.
 
 .. table:: Comparison between different rounding modes for division and modulo cells.
 

docs/source/cell/word_unary.rst

@@ -38,11 +38,11 @@ For the unary cells that output a logical value (`$reduce_and`, `$reduce_or`,
 ``Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and only
 the least significant bit varies.
 
-Note that `$reduce_or` and `$reduce_bool` actually represent the same logic
+Note that `$reduce_or` and `$reduce_bool` generally represent the same logic
-function. But the HDL frontends generate them in different situations. A
+function. But the `read_verilog` frontend will generate them in different
-`$reduce_or` cell is generated when the prefix ``|`` operator is being used. A
+situations. A `$reduce_or` cell is generated when the prefix ``|`` operator is
-`$reduce_bool` cell is generated when a bit vector is used as a condition in an
+being used. A `$reduce_bool` cell is generated when a bit vector is used as a
-``if``-statement or ``?:``-expression.
+condition in an ``if``-statement or ``?:``-expression.
 
 .. autocellgroup:: unary
    :members:

docs/source/cell_index.rst

@@ -1,7 +1,11 @@
 Internal cell library
 =====================
 
-.. todo:: brief overview of internal cell library
+The intermediate language used by Yosys (RTLIL) represents logic and memory with
+a series of cells. This section provides details for those cells, breaking them
+down into two major categories: coarse-grain word-level cells; and fine-grain
+gate-level cells. An additional section contains a list of properties which may
+be shared across multiple cells.
 
 .. toctree::
    :maxdepth: 2

techlibs/common/simlib.v

@@ -528,10 +528,10 @@ endmodule
 // --------------------------------------------------------
 
 //* ver 2
-//* title Indexed part-select
+//* title Variable shifter
 //* group binary
-//* tags x-output
+//- Performs a right logical shift if the second operand is positive (or
-//- Same as the `$shift` cell, but fills with 'x'.
+//- unsigned), and a left logical shift if it is negative.
 //-
 
 module \$shift (A, B, Y);
@@ -567,10 +567,10 @@ endmodule
 // --------------------------------------------------------
 
 //* ver 2
-//* title Variable shifter
+//* title Indexed part-select
 //* group binary
-//- Performs a right logical shift if the second operand is positive (or
+//* tags x-output
-//- unsigned), and a left logical shift if it is negative.
+//- Same as the `$shift` cell, but fills with 'x'.
 //-
 
 module \$shiftx (A, B, Y);