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Docs: Comments from @jix

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- Unswap shift/shiftx
- Add brief overview to cell lib
- Clarify $div cell B input
- Clarify unary operators
- What is $modfloor
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Krystine Sherwin 2024-09-16 20:38:37 +12:00
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10
docs/source/cell/word_unary.rst
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@ -38,11 +38,11 @@ For the unary cells that output a logical value (`$reduce_and`, `$reduce_or`,
``Y_WIDTH`` parameter is greater than 1, the output is zero-extended, and only
the least significant bit varies.
Note that `$reduce_or` and `$reduce_bool` actually represent the same logic
function. But the HDL frontends generate them in different situations. A
`$reduce_or` cell is generated when the prefix ``|`` operator is being used. A
`$reduce_bool` cell is generated when a bit vector is used as a condition in an
``if``-statement or ``?:``-expression.
Note that `$reduce_or` and `$reduce_bool` generally represent the same logic
function. But the `read_verilog` frontend will generate them in different
situations. A `$reduce_or` cell is generated when the prefix ``|`` operator is
being used. A `$reduce_bool` cell is generated when a bit vector is used as a
condition in an ``if``-statement or ``?:``-expression.
.. autocellgroup:: unary
:members: