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Quick fix

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This commit is contained in:
Miodrag Milanovic 2022-02-28 11:40:06 +01:00
parent 56b968f61c
commit dfd4c81eac
1 changed files with 2 additions and 0 deletions
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2
passes/sat/sim.cc
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@ -1304,6 +1304,8 @@ struct SimWorker : SimShared
state = 3; state = 3;
break; break;
default: default:
log("Simulating cycle %d.\n", cycle);
top->setState(inputs, line);
if (cycle) { if (cycle) {
set_inports(clock, State::S1); set_inports(clock, State::S1);
set_inports(clockn, State::S0); set_inports(clockn, State::S0);