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	Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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					 5 changed files with 39 additions and 3 deletions
				
			
		|  | @ -47,16 +47,20 @@ struct IlangFrontend : public Frontend { | ||||||
| 		log("    -nooverwrite\n"); | 		log("    -nooverwrite\n"); | ||||||
| 		log("        ignore re-definitions of modules. (the default behavior is to\n"); | 		log("        ignore re-definitions of modules. (the default behavior is to\n"); | ||||||
| 		log("        create an error message if the existing module is not a blackbox\n"); | 		log("        create an error message if the existing module is not a blackbox\n"); | ||||||
| 		log("        module, and overwrite the existing module if it is  a blackbox module.)\n"); | 		log("        module, and overwrite the existing module if it is a blackbox module.)\n"); | ||||||
| 		log("\n"); | 		log("\n"); | ||||||
| 		log("    -overwrite\n"); | 		log("    -overwrite\n"); | ||||||
| 		log("        overwrite existing modules with the same name\n"); | 		log("        overwrite existing modules with the same name\n"); | ||||||
| 		log("\n"); | 		log("\n"); | ||||||
|  | 		log("    -lib\n"); | ||||||
|  | 		log("        only create empty blackbox modules\n"); | ||||||
|  | 		log("\n"); | ||||||
| 	} | 	} | ||||||
| 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE | 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE | ||||||
| 	{ | 	{ | ||||||
| 		ILANG_FRONTEND::flag_nooverwrite = false; | 		ILANG_FRONTEND::flag_nooverwrite = false; | ||||||
| 		ILANG_FRONTEND::flag_overwrite = false; | 		ILANG_FRONTEND::flag_overwrite = false; | ||||||
|  | 		ILANG_FRONTEND::flag_lib = false; | ||||||
| 
 | 
 | ||||||
| 		log_header(design, "Executing ILANG frontend.\n"); | 		log_header(design, "Executing ILANG frontend.\n"); | ||||||
| 
 | 
 | ||||||
|  | @ -73,6 +77,10 @@ struct IlangFrontend : public Frontend { | ||||||
| 				ILANG_FRONTEND::flag_overwrite = true; | 				ILANG_FRONTEND::flag_overwrite = true; | ||||||
| 				continue; | 				continue; | ||||||
| 			} | 			} | ||||||
|  | 			if (arg == "-lib") { | ||||||
|  | 				ILANG_FRONTEND::flag_lib = true; | ||||||
|  | 				continue; | ||||||
|  | 			} | ||||||
| 			break; | 			break; | ||||||
| 		} | 		} | ||||||
| 		extra_args(f, filename, args, argidx); | 		extra_args(f, filename, args, argidx); | ||||||
|  |  | ||||||
|  | @ -34,6 +34,7 @@ namespace ILANG_FRONTEND { | ||||||
| 	extern RTLIL::Design *current_design; | 	extern RTLIL::Design *current_design; | ||||||
| 	extern bool flag_nooverwrite; | 	extern bool flag_nooverwrite; | ||||||
| 	extern bool flag_overwrite; | 	extern bool flag_overwrite; | ||||||
|  | 	extern bool flag_lib; | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
| YOSYS_NAMESPACE_END | YOSYS_NAMESPACE_END | ||||||
|  |  | ||||||
|  | @ -37,7 +37,7 @@ namespace ILANG_FRONTEND { | ||||||
| 	std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack; | 	std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack; | ||||||
| 	std::vector<RTLIL::CaseRule*> case_stack; | 	std::vector<RTLIL::CaseRule*> case_stack; | ||||||
| 	dict<RTLIL::IdString, RTLIL::Const> attrbuf; | 	dict<RTLIL::IdString, RTLIL::Const> attrbuf; | ||||||
| 	bool flag_nooverwrite, flag_overwrite; | 	bool flag_nooverwrite, flag_overwrite, flag_lib; | ||||||
| 	bool delete_current_module; | 	bool delete_current_module; | ||||||
| } | } | ||||||
| using namespace ILANG_FRONTEND; | using namespace ILANG_FRONTEND; | ||||||
|  | @ -98,7 +98,7 @@ module: | ||||||
| 		delete_current_module = false; | 		delete_current_module = false; | ||||||
| 		if (current_design->has($2)) { | 		if (current_design->has($2)) { | ||||||
| 			RTLIL::Module *existing_mod = current_design->module($2); | 			RTLIL::Module *existing_mod = current_design->module($2); | ||||||
| 			if (!flag_overwrite && attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()) { | 			if (!flag_overwrite && (flag_lib || (attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()))) { | ||||||
| 				log("Ignoring blackbox re-definition of module %s.\n", $2); | 				log("Ignoring blackbox re-definition of module %s.\n", $2); | ||||||
| 				delete_current_module = true; | 				delete_current_module = true; | ||||||
| 			} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { | 			} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { | ||||||
|  | @ -124,6 +124,8 @@ module: | ||||||
| 		current_module->fixup_ports(); | 		current_module->fixup_ports(); | ||||||
| 		if (delete_current_module) | 		if (delete_current_module) | ||||||
| 			delete current_module; | 			delete current_module; | ||||||
|  | 		else if (flag_lib) | ||||||
|  | 			current_module->makeblackbox(); | ||||||
| 		current_module = nullptr; | 		current_module = nullptr; | ||||||
| 	} EOL; | 	} EOL; | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -641,6 +641,30 @@ RTLIL::Module::~Module() | ||||||
| 		delete it->second; | 		delete it->second; | ||||||
| } | } | ||||||
| 
 | 
 | ||||||
|  | void RTLIL::Module::makeblackbox() | ||||||
|  | { | ||||||
|  | 	pool<RTLIL::Wire*> delwires; | ||||||
|  | 
 | ||||||
|  | 	for (auto it = wires_.begin(); it != wires_.end(); ++it) | ||||||
|  | 		if (!it->second->port_input && !it->second->port_output) | ||||||
|  | 			delwires.insert(it->second); | ||||||
|  | 
 | ||||||
|  | 	for (auto it = memories.begin(); it != memories.end(); ++it) | ||||||
|  | 		delete it->second; | ||||||
|  | 	memories.clear(); | ||||||
|  | 
 | ||||||
|  | 	for (auto it = cells_.begin(); it != cells_.end(); ++it) | ||||||
|  | 		delete it->second; | ||||||
|  | 	cells_.clear(); | ||||||
|  | 
 | ||||||
|  | 	for (auto it = processes.begin(); it != processes.end(); ++it) | ||||||
|  | 		delete it->second; | ||||||
|  | 	processes.clear(); | ||||||
|  | 
 | ||||||
|  | 	remove(delwires); | ||||||
|  | 	set_bool_attribute("\\blackbox"); | ||||||
|  | } | ||||||
|  | 
 | ||||||
| void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>) | void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>) | ||||||
| { | { | ||||||
| 	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); | 	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); | ||||||
|  |  | ||||||
|  | @ -976,6 +976,7 @@ public: | ||||||
| 	virtual void sort(); | 	virtual void sort(); | ||||||
| 	virtual void check(); | 	virtual void check(); | ||||||
| 	virtual void optimize(); | 	virtual void optimize(); | ||||||
|  | 	virtual void makeblackbox(); | ||||||
| 
 | 
 | ||||||
| 	void connect(const RTLIL::SigSig &conn); | 	void connect(const RTLIL::SigSig &conn); | ||||||
| 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); | 	void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); | ||||||
|  |  | ||||||
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